intel/e7505,i82801dx: Fix SMM_ASEG lock

In our codebase, this is only coupled with intel/e7505.
The PCI registers reference here were for intel/i945.

Also aseg_smm_lock() was previously not called.

Change-Id: I21d991c8c2f5c2dde1f148fd80963e39d9836d3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34149
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/e7505/e7505.h

@@ -42,6 +42,8 @@
 #define DRC		0x7C	/* DRAM Controller Mode register, 32 bit */
 #define DRDCTL		0x80	/* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
 #define CKDIS		0x8C	/* Clock disable register, 8 bit */
+#define SMRAMC		0x9D
+#define ESMRAMC		0x9E
 #define APSIZE		0xB4
 #define TOLM		0xC4	/* Top of Low Memory register, 16 bit */
 #define REMAPBASE	0xC6	/* Remap Base Address register, 16 bit */

src/northbridge/intel/e7505/memmap.c

@@ -35,6 +35,14 @@ void *cbmem_top(void)
 	return (void *)tolm;
 }
 
+void northbridge_write_smram(u8 smram);
+
+void northbridge_write_smram(u8 smram)
+{
+	pci_devfn_t mch = PCI_DEV(0, 0, 0);
+	pci_write_config8(mch, SMRAMC, smram);
+}
+
 /* platform_enter_postcar() determines the stack to use after
  * cache-as-ram is torn down as well as the MTRR settings to use,
  * and continues execution in postcar stage. */

src/southbridge/intel/i82801dx/i82801dx.h

@@ -37,6 +37,9 @@ extern void i82801dx_enable(struct device *dev);
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
 #endif
+
+void aseg_smm_lock(void);
+
 #endif
 
 #define DEBUG_PERIODIC_SMIS 0

src/southbridge/intel/i82801dx/lpc.c

@@ -299,6 +299,12 @@ static void lpc_init(struct device *dev)
 
 	/* Initialize the High Precision Event Timers */
 	enable_hpet(dev);
+
+	/* Don't allow evil boot loaders, kernels, or
+	 * userspace applications to deceive us:
+	 */
+	if (CONFIG(HAVE_SMI_HANDLER))
+		aseg_smm_lock();
 }
 
 static void i82801dx_lpc_read_resources(struct device *dev)

src/southbridge/intel/i82801dx/smi.c

@@ -26,8 +26,10 @@
 #include <string.h>
 #include "i82801dx.h"
 
-/* I945 */
-#define SMRAM		0x90
+
+void northbridge_write_smram(u8 smram);
+
+/* For intel/e7505. */
 #define   D_OPEN	(1 << 6)
 #define   D_CLS		(1 << 5)
 #define   D_LCK		(1 << 4)
@@ -317,18 +319,10 @@ static void smm_relocate(void)
 
 static void smm_install(void)
 {
-	/* enable the SMM memory window */
-	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
-				D_OPEN | G_SMRAME | C_BASE_SEG);
-
 	/* copy the real SMM handler */
 	memcpy((void *)0xa0000, _binary_smm_start,
 		_binary_smm_end - _binary_smm_start);
 	wbinvd();
-
-	/* close the SMM memory window and enable normal SMM */
-	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
-			G_SMRAME | C_BASE_SEG);
 }
 
 void smm_init(void)
@@ -348,15 +342,14 @@ void smm_init_completion(void)
 	restore_default_smm_area(default_smm_area);
 }
 
-void smm_lock(void)
+void aseg_smm_lock(void)
 {
 	/* LOCK the SMM memory window and enable normal SMM.
 	 * After running this function, only a full reset can
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
-			D_LCK | G_SMRAME | C_BASE_SEG);
+	northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG);
 }
 
 void smm_setup_structures(void *gnvs, void *tcg, void *smi1)