arm/exynos: Allow DRAM controller to be initialized without clearing RAM content.
To support suspend/resume, PHY control must be reset only on normal boot path. So add a new param "mem_reset" to specify that. Verified to boot successfully on Google/Snow. Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3128 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -61,7 +61,8 @@ static void reset_phy_ctrl(void)
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udelay(500);
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}
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
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int mem_reset)
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{
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unsigned int val;
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struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
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@ -71,9 +72,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
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phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
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phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
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dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
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printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: ");
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reset_phy_ctrl();
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printk(BIOS_SPEW, "done\n");
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if (mem_reset) {
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printk(BIOS_SPEW, "%s: reset phy: ", __func__);
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reset_phy_ctrl();
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printk(BIOS_SPEW, "done\n");
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} else {
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printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__);
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}
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/* Set Impedance Output Driver */
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printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n");
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@ -702,9 +702,11 @@ void mem_ctrl_init(void);
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* which the DMC uses to decide how to split a memory
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* chunk into smaller chunks to support concurrent
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* accesses; may vary across boards.
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* @param mem_reset Reset memory during initialization.
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* @return 0 if ok, SETUP_ERR_... if there is a problem
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*/
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
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int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
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int mem_reset);
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void tzpc_init(void);
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/*
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@ -184,7 +184,7 @@ void main(void)
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mem->mpll_mdiv,
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mem->frequency_mhz);
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ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
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ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1);
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if (ret) {
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printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
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ret);
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