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arm/exynos: Allow DRAM controller to be initialized without clearing RAM content. 

To support suspend/resume, PHY control must be reset only on normal boot
path.  So add a new param "mem_reset" to specify that.

Verified to boot successfully on Google/Snow.

Change-Id: Id49bc6c6239cf71a67ba091092dd3ebf18e83e33
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/3128
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Hung-Te Lin 2013-04-25 16:14:19 +08:00 committed by Ronald G. Minnich
parent 175ad4aa6e
commit 55c753d3a9
3 changed files with 14 additions and 6 deletions
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10
src/cpu/samsung/exynos5250/dmc_init_ddr3.c
View File

@ -61,7 +61,8 @@ static void reset_phy_ctrl(void)
udelay(500);
}
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
int mem_reset)
{
unsigned int val;
struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
@ -71,9 +72,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)
phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: reset phy: ");
if (mem_reset) {
printk(BIOS_SPEW, "%s: reset phy: ", __func__);
reset_phy_ctrl();
printk(BIOS_SPEW, "done\n");
} else {
printk(BIOS_SPEW, "%s: skip mem_reset.\n", __func__);
}
/* Set Impedance Output Driver */
printk(BIOS_SPEW, "ddr3_mem_ctrl_init: Set Impedance Output Driver\n");

4
src/cpu/samsung/exynos5250/setup.h
View File

@ -702,9 +702,11 @@ void mem_ctrl_init(void);
* which the DMC uses to decide how to split a memory
* chunk into smaller chunks to support concurrent
* accesses; may vary across boards.
* @param mem_reset Reset memory during initialization.
* @return 0 if ok, SETUP_ERR_... if there is a problem
*/
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size);
int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
int mem_reset);
void tzpc_init(void);
/*

2
src/mainboard/google/snow/romstage.c
View File

@ -184,7 +184,7 @@ void main(void)
mem->mpll_mdiv,
mem->frequency_mhz);
ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE, 1);
if (ret) {
printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
ret);