mb/google/zork: Switch zork to use spd_tools
Switch all zork boards to use generated generic SPDs from spd_tools. HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was removed. picasso/Makefile.inc was updated to populate the 2nd APCB channel based on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd entires with _x1/_x2. Command to generate files: $ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do n=$(basename ${b}); if [ "${n}" = "baseboard" ]; then continue fi go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \ src/mainboard/google/zork/variants/${n}/spd \ src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt done BUG=b:162939176 TEST=Boot ezkinil and dalboz check dmidecod -t17 Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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# Generic DDR4 SPD template
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# Fields that are not required should be set to zero
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# CRC will be calculated when generating SPDs from this template, so no need
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# to update here
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# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
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23
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# SPD Revision (Rev. 1.1)
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11
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# Key Byte / DRAM Device Type (DDR4 SDRAM)
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0C
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# Key Byte / Module Type (nECC SO-DIMM)
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03
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# SDRAM Density and Banks (2BG/4BK/8Gb)
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45
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# SDRAM Addressing (16/10)
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21
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# Primary SDRAM Package Type (Flipchip SDP)
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00
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# SDRAM Optional Features (Unlimited MAC)
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08
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# SDRAM Thermal and Refresh Options (Reserved)
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00
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# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
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60
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# Secondary SDRAM Package Type
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00
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# Module Nominal Volatage, VDD (1.2V)
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03
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# Module Organization
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01
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# Module Memory Bus Width (LP/x64)
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03
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# Module Thermal Sensor (Termal sensor not incorporated)
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00
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# Extended Module Type (Reserved)
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00
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# Reserved
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00
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# Timebases (MTB : 125ps, FTB : 1ps)
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00
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# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
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06
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# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
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0D
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# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
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F8
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# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
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3F
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# CAS Latencies Supported, Third Byte
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00
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# CAS Latencies Supported, Fourth Byte
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00
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# Minimum CAS Latency Time (tAAmin) (13.75ns)
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6E
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# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
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6E
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# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
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6E
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# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
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11
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# tRASmin, Least Significant Byte (32ns)
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00
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# tRCmin, Least Significant Byte (45.75ns)
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6E
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# tRFC1min, LSB (350ns)
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F0
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# tRFC1min, MSB (350ns)
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0A
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# tRFC2min, LSB (260ns)
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20
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# tRFC2min, MSB (260ns)
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08
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# tRFC4min, LSB (160ns)
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00
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# tRFC4min, MSB (160ns)
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05
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# Upper Nibble for tFAW (30ns)
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00
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# tFAWmin LSB (30ns)
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F0
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# tRRD_Smin (5.3ns)
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2B
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# tRRD_L min (6.40ns)
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34
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# tCCD_Lmin, same bank group (5ns)
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28
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# tWRmin Upper Nibbles (15ns)
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00
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# tWRmin (15ns)
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78
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# tWTRmin Upper Nibbles (2.5ns/7.5ns)
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00
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# tWTR_Smin (2.5ns)
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14
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|
||||
# tWTR_Lmin (7.5ns)
|
||||
3C
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ0-3)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ4-7)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ8-11)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ12-15)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ16-19)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ20-23)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ24-27)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ28-31)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB0-3)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB4-7)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ32-35)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ36-39)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ40-43)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ44-47)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ48-51)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ52-55)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ56-59)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ60-63)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00
|
||||
|
||||
# Fine offset for tCCD_Lmin, same bank group (5ns)
|
||||
00
|
||||
|
||||
# tRRD_L min offset (6.40ns)
|
||||
9C
|
||||
|
||||
# tRRD_Smin offset (blank)
|
||||
00
|
||||
|
||||
# Fine offset for tRCmin (45.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRPmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRCDmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tAAmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tCKAVGmax (1.6ns)
|
||||
E7
|
||||
|
||||
# Fine offset for tCKAVGmin (0.75ns)
|
||||
00
|
||||
|
||||
# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
|
||||
00
|
||||
|
||||
# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
|
||||
00
|
||||
|
||||
# RC Extension, Module Nominal Height
|
||||
00
|
||||
|
||||
# Module Maximum Thickness
|
||||
00
|
||||
|
||||
# Reference Raw Card Used
|
||||
00
|
||||
|
||||
# Address Mapping from Edge Connector to DRAM (Standard)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved (Must be coded as 0x00)
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00
|
||||
|
||||
# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
|
||||
00
|
||||
|
||||
# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Module Manufacturer's ID Code, LSB (blank)
|
||||
00
|
||||
|
||||
# Module Manufacturer's ID Code, MSB (blank)
|
||||
00
|
||||
|
||||
# Module Manufacturing Location (blank)
|
||||
00
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Part Number (blank)
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00
|
||||
|
||||
# Module Revision Code (Revision 0)
|
||||
00
|
||||
|
||||
# DRAM Manufacturer's ID code, LSB (blank)
|
||||
00
|
||||
|
||||
# DRAM Manufacturer's ID code, MSB (blank)
|
||||
00
|
||||
|
||||
# DRAM Stepping (Undefined)
|
||||
00
|
||||
|
||||
# Module Manufacturer's Specific Data (blank)
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved
|
||||
00 00
|
||||
|
||||
# End User Programmable
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -2,28 +2,3 @@
|
|||
|
||||
# This directory
|
||||
SPD_SOURCES_DIR := src/mainboard/$(MAINBOARDDIR)/spd
|
||||
|
||||
# Ordered List of APCB entries, up to 16.
|
||||
# Entries should match this pattern {NAME}_x{1,2}
|
||||
# There should be a matching SPD hex file in SPD_SOURCES_DIR
|
||||
# matching the pattern {NAME}.spd.hex
|
||||
# The _x{1,2} suffix denotes single or dual channel
|
||||
# TODO: Remove channel suffix when b:141434940 is fixed
|
||||
# Alternatively, generated APCBs stored at
|
||||
# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
|
||||
APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0001
|
||||
APCB_SOURCES += empty # 0b0010
|
||||
APCB_SOURCES += empty # 0b0011
|
||||
APCB_SOURCES += empty # 0b0100
|
||||
APCB_SOURCES += empty # 0b0101
|
||||
APCB_SOURCES += empty # 0b0110
|
||||
APCB_SOURCES += empty # 0b0111
|
||||
APCB_SOURCES += empty # 0b1000
|
||||
APCB_SOURCES += empty # 0b1001
|
||||
APCB_SOURCES += empty # 0b1010
|
||||
APCB_SOURCES += empty # 0b1011
|
||||
APCB_SOURCES += empty # 0b1100
|
||||
APCB_SOURCES += empty # 0b1101
|
||||
APCB_SOURCES += empty # 0b1110
|
||||
APCB_SOURCES += empty # 0b1111
|
||||
|
|
|
@ -1,33 +0,0 @@
|
|||
#Empty SPD - placeholder file
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,331 +0,0 @@
|
|||
# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
|
||||
23
|
||||
|
||||
# SPD Revision (Rev. 1.1)
|
||||
11
|
||||
|
||||
# Key Byte / DRAM Device Type (DDR4 SDRAM)
|
||||
0C
|
||||
|
||||
# Key Byte / Module Type (nECC SO-DIMM)
|
||||
03
|
||||
|
||||
# SDRAM Density and Banks (2BG/4BK/8Gb)
|
||||
45
|
||||
|
||||
# SDRAM Addressing (16/10)
|
||||
21
|
||||
|
||||
# Primary SDRAM Package Type (Flipchip SDP)
|
||||
00
|
||||
|
||||
# SDRAM Optional Features (Unlimited MAC)
|
||||
08
|
||||
|
||||
# SDRAM Thermal and Refresh Options (Reserved)
|
||||
00
|
||||
|
||||
# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
|
||||
60
|
||||
|
||||
# Secondary SDRAM Package Type
|
||||
00
|
||||
|
||||
# Module Nominal Volatage, VDD (1.2V)
|
||||
03
|
||||
|
||||
# Module Organization (1Rx16)
|
||||
02
|
||||
|
||||
# Module Memory Bus Width (LP/x64)
|
||||
03
|
||||
|
||||
# Module Thermal Sensor (Termal sensor not incorporated)
|
||||
00
|
||||
|
||||
# Extended Module Type (Reserved)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00
|
||||
|
||||
# Timebases (MTB : 125ps, FTB : 1ps)
|
||||
00
|
||||
|
||||
# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
|
||||
06
|
||||
|
||||
# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
|
||||
0D
|
||||
|
||||
# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
|
||||
F8
|
||||
|
||||
# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
|
||||
3F
|
||||
|
||||
# CAS Latencies Supported, Third Byte
|
||||
00
|
||||
|
||||
# CAS Latencies Supported, Fourth Byte
|
||||
00
|
||||
|
||||
# Minimum CAS Latency Time (tAAmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
|
||||
11
|
||||
|
||||
# tRASmin, Least Significant Byte (32ns)
|
||||
00
|
||||
|
||||
# tRCmin, Least Significant Byte (45.75ns)
|
||||
6E
|
||||
|
||||
# tRFC1min, LSB (350ns)
|
||||
F0
|
||||
|
||||
# tRFC1min, MSB (350ns)
|
||||
0A
|
||||
|
||||
# tRFC2min, LSB (260ns)
|
||||
20
|
||||
|
||||
# tRFC2min, MSB (260ns)
|
||||
08
|
||||
|
||||
# tRFC4min, LSB (160ns)
|
||||
00
|
||||
|
||||
# tRFC4min, MSB (160ns)
|
||||
05
|
||||
|
||||
# Upper Nibble for tFAW (30ns)
|
||||
00
|
||||
|
||||
# tFAWmin LSB (30ns)
|
||||
F0
|
||||
|
||||
# tRRD_Smin (5.3ns)
|
||||
2B
|
||||
|
||||
# tRRD_L min (6.40ns)
|
||||
34
|
||||
|
||||
# tCCD_Lmin, same bank group (5ns)
|
||||
28
|
||||
|
||||
# tWRmin Upper Nibbles (15ns)
|
||||
00
|
||||
|
||||
# tWRmin (15ns)
|
||||
78
|
||||
|
||||
# tWTRmin Upper Nibbles (2.5ns/7.5ns)
|
||||
00
|
||||
|
||||
# tWTR_Smin (2.5ns)
|
||||
14
|
||||
|
||||
# tWTR_Lmin (7.5ns)
|
||||
3C
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ0-3)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ4-7)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ8-11)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ12-15)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ16-19)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ20-23)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ24-27)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ28-31)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB0-3)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB4-7)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ32-35)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ36-39)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ40-43)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ44-47)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ48-51)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ52-55)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ56-59)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ60-63)
|
||||
35
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00
|
||||
|
||||
# Fine offset for tCCD_Lmin, same bank group (5ns)
|
||||
00
|
||||
|
||||
# tRRD_L min offset (6.40ns)
|
||||
9C
|
||||
|
||||
# tRRD_Smin offset (5.3ns)
|
||||
B5
|
||||
|
||||
# Fine offset for tRCmin (45.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRPmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRCDmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tAAmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tCKAVGmax (1.6ns)
|
||||
E7
|
||||
|
||||
# Fine offset for tCKAVGmin (0.75ns)
|
||||
00
|
||||
|
||||
# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
|
||||
87
|
||||
|
||||
# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
|
||||
2E
|
||||
|
||||
# RC Extention, Module Nominal Height (30.00)
|
||||
0F
|
||||
|
||||
# Module Maximum Thickness (1.0/1.2)
|
||||
01
|
||||
|
||||
# Reference Raw Card Used (C0)
|
||||
02
|
||||
|
||||
# Address Mapping from Edge Connector to DRAM (Standard)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved (Must be coded as 0x00)
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00
|
||||
|
||||
# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
|
||||
C0
|
||||
|
||||
# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
|
||||
E2
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Module Manufacturer's ID Code, LSB (SK hynix)
|
||||
80
|
||||
|
||||
# Module Manufacturer's ID Code, MSB (SK hynix)
|
||||
AD
|
||||
|
||||
# Module Manufacturing Location (SK hynix (Icheon))
|
||||
01
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Part Number (H5AN8G6NCJR-VKC )
|
||||
48 35 41 4E 38 47 36 4E 43 4A 52 2D 56 4B 43 20
|
||||
20 20 20 20
|
||||
|
||||
# Module Revision Code (Revision 0)
|
||||
00
|
||||
|
||||
# DRAM Manufacturer's ID code, LSB (SK hynix)
|
||||
80
|
||||
|
||||
# DRAM Manufacturer's ID code, MSB (SK hynix)
|
||||
AD
|
||||
|
||||
# DRAM Stepping (Undefined)
|
||||
FF
|
||||
|
||||
# Module Manufacturer's Specific Data
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 DD
|
||||
|
||||
# Reserved
|
||||
00 00
|
||||
|
||||
# End User Programmable
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Hynix-H5AN8G6NCJR-XNC
|
||||
23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20
|
||||
0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53
|
||||
36 43 4A 52 36 4A 2D 58 4E 20 20 20 20 00 80 AD
|
||||
FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Hynix H5AN8G6NDJR-XNC
|
||||
23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20
|
||||
0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 AD 01 00 00 00 00 00 00 48 35 41 4E 38 47 36
|
||||
4E 44 4A 52 2D 58 4E 43 20 20 20 20 20 00 80 AD
|
||||
FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Hynix H5ANAG6NCMR-VKC
|
||||
23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00
|
||||
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
|
||||
16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE
|
||||
0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53
|
||||
36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD
|
||||
FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Hynix H5ANAG6NCMR-XNC
|
||||
23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00
|
||||
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 A8 14 28 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 C0 6E
|
||||
0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 AD 01 00 00 00 00 00 00 48 35 41 4E 41 47 36
|
||||
4E 43 4D 52 2D 58 4E 43 20 20 20 20 20 00 80 AD
|
||||
FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 DD 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,331 +0,0 @@
|
|||
# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
|
||||
23
|
||||
|
||||
# SPD Revision (Rev. 1.1)
|
||||
11
|
||||
|
||||
# Key Byte / DRAM Device Type (DDR4 SDRAM)
|
||||
0C
|
||||
|
||||
# Key Byte / Module Type (nECC SO-DIMM)
|
||||
03
|
||||
|
||||
# SDRAM Density and Banks (2BG/4BK/8Gb)
|
||||
45
|
||||
|
||||
# SDRAM Addressing (16/10)
|
||||
21
|
||||
|
||||
# Primary SDRAM Package Type (Flipchip SDP)
|
||||
00
|
||||
|
||||
# SDRAM Optional Features (Unlimited MAC)
|
||||
08
|
||||
|
||||
# SDRAM Thermal and Refresh Options (Reserved)
|
||||
00
|
||||
|
||||
# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
|
||||
60
|
||||
|
||||
# Secondary SDRAM Package Type
|
||||
00
|
||||
|
||||
# Module Nominal Volatage, VDD (1.2V)
|
||||
03
|
||||
|
||||
# Module Organization (1Rx16)
|
||||
02
|
||||
|
||||
# Module Memory Bus Width (LP/x64)
|
||||
03
|
||||
|
||||
# Module Thermal Sensor (Termal sensor not incorporated)
|
||||
00
|
||||
|
||||
# Extended Module Type (Reserved)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00
|
||||
|
||||
# Timebases (MTB : 125ps, FTB : 1ps)
|
||||
00
|
||||
|
||||
# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
|
||||
06
|
||||
|
||||
# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
|
||||
0D
|
||||
|
||||
# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
|
||||
F8
|
||||
|
||||
# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
|
||||
3F
|
||||
|
||||
# CAS Latencies Supported, Third Byte
|
||||
00
|
||||
|
||||
# CAS Latencies Supported, Fourth Byte
|
||||
00
|
||||
|
||||
# Minimum CAS Latency Time (tAAmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
|
||||
11
|
||||
|
||||
# tRASmin, Least Significant Byte (32ns)
|
||||
00
|
||||
|
||||
# tRCmin, Least Significant Byte (45.75ns)
|
||||
6E
|
||||
|
||||
# tRFC1min, LSB (350ns)
|
||||
F0
|
||||
|
||||
# tRFC1min, MSB (350ns)
|
||||
0A
|
||||
|
||||
# tRFC2min, LSB (260ns)
|
||||
20
|
||||
|
||||
# tRFC2min, MSB (260ns)
|
||||
08
|
||||
|
||||
# tRFC4min, LSB (160ns)
|
||||
00
|
||||
|
||||
# tRFC4min, MSB (160ns)
|
||||
05
|
||||
|
||||
# Upper Nibble for tFAW (30ns)
|
||||
00
|
||||
|
||||
# tFAWmin LSB (30ns)
|
||||
F0
|
||||
|
||||
# tRRD_Smin (5.3ns)
|
||||
2B
|
||||
|
||||
# tRRD_L min (6.40ns)
|
||||
34
|
||||
|
||||
# tCCD_Lmin, same bank group (5ns)
|
||||
28
|
||||
|
||||
# tWRmin Upper Nibbles (15ns)
|
||||
00
|
||||
|
||||
# tWRmin (15ns)
|
||||
78
|
||||
|
||||
# tWTRmin Upper Nibbles (2.5ns/7.5ns)
|
||||
00
|
||||
|
||||
# tWTR_Smin (2.5ns)
|
||||
14
|
||||
|
||||
# tWTR_Lmin (7.5ns)
|
||||
3C
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ0-3)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ4-7)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ8-11)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ12-15)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ16-19)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ20-23)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ24-27)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ28-31)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB0-3)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB4-7)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ32-35)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ36-39)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ40-43)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ44-47)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ48-51)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ52-55)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ56-59)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ60-63)
|
||||
35
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00
|
||||
|
||||
# Fine offset for tCCD_Lmin, same bank group (5ns)
|
||||
00
|
||||
|
||||
# tRRD_L min offset (6.40ns)
|
||||
9C
|
||||
|
||||
# tRRD_Smin offset (5.3ns)
|
||||
B5
|
||||
|
||||
# Fine offset for tRCmin (45.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRPmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRCDmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tAAmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tCKAVGmax (1.6ns)
|
||||
E7
|
||||
|
||||
# Fine offset for tCKAVGmin (0.75ns)
|
||||
00
|
||||
|
||||
# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
|
||||
87
|
||||
|
||||
# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
|
||||
2E
|
||||
|
||||
# RC Extention, Module Nominal Height (30.00)
|
||||
0F
|
||||
|
||||
# Module Maximum Thickness (1.0/1.2)
|
||||
01
|
||||
|
||||
# Reference Raw Card Used (C0)
|
||||
02
|
||||
|
||||
# Address Mapping from Edge Connector to DRAM (Standard)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved (Must be coded as 0x00)
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00
|
||||
|
||||
# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
|
||||
C0
|
||||
|
||||
# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
|
||||
E2
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Module Manufacturer's ID Code, LSB (SK hynix)
|
||||
80
|
||||
|
||||
# Module Manufacturer's ID Code, MSB (SK hynix)
|
||||
AD
|
||||
|
||||
# Module Manufacturing Location (SK hynix (Icheon))
|
||||
01
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Part Number (HMA851S6CJR6N-VK )
|
||||
48 4D 41 38 35 31 53 36 43 4A 52 36 4E 2D 56 4B
|
||||
20 20 20 20
|
||||
|
||||
# Module Revision Code (Revision 0)
|
||||
00
|
||||
|
||||
# DRAM Manufacturer's ID code, LSB (SK hynix)
|
||||
80
|
||||
|
||||
# DRAM Manufacturer's ID code, MSB (SK hynix)
|
||||
AD
|
||||
|
||||
# DRAM Stepping (Undefined)
|
||||
FF
|
||||
|
||||
# Module Manufacturer's Specific Data
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 DD
|
||||
|
||||
# Reserved
|
||||
00 00
|
||||
|
||||
# End User Programmable
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,331 +0,0 @@
|
|||
# Number of Serial PD Bytes Written / SPD Device Size (SPD Bytes Used : 384 / SPD Bytes Total : 512)
|
||||
23
|
||||
|
||||
# SPD Revision (Rev. 1.1)
|
||||
11
|
||||
|
||||
# Key Byte / DRAM Device Type (DDR4 SDRAM)
|
||||
0C
|
||||
|
||||
# Key Byte / Module Type (nECC SO-DIMM)
|
||||
03
|
||||
|
||||
# SDRAM Density and Banks (2BG/4BK/8Gb)
|
||||
45
|
||||
|
||||
# SDRAM Addressing (16/10)
|
||||
21
|
||||
|
||||
# Primary SDRAM Package Type (DDP)
|
||||
91
|
||||
|
||||
# SDRAM Optional Features (Unlimited MAC)
|
||||
08
|
||||
|
||||
# SDRAM Thermal and Refresh Options (Reserved)
|
||||
00
|
||||
|
||||
# Other SDRAM Optional Features (PPR) (hPPR, sPPR supported)
|
||||
60
|
||||
|
||||
# Secondary SDRAM Package Type
|
||||
00
|
||||
|
||||
# Module Nominal Volatage, VDD (1.2V)
|
||||
03
|
||||
|
||||
# Module Organization (1Rx8)
|
||||
01
|
||||
|
||||
# Module Memory Bus Width (LP/x64)
|
||||
03
|
||||
|
||||
# Module Thermal Sensor (Termal sensor not incorporated)
|
||||
00
|
||||
|
||||
# Extended Module Type (Reserved)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00
|
||||
|
||||
# Timebases (MTB : 125ps, FTB : 1ps)
|
||||
00
|
||||
|
||||
# SDRAM Minimum Cycle Time (tCKAVGmin) (0.75ns)
|
||||
06
|
||||
|
||||
# SDRAM Maximum Cycle Time (tCKAVGmax) (1.6ns)
|
||||
0D
|
||||
|
||||
# CAS Latencies Supported, First Byte (10, 11, 12, 13, 14)
|
||||
F8
|
||||
|
||||
# CAS Latencies Supported, Second Byte (15, 16, 17, 18, 19, 20)
|
||||
3F
|
||||
|
||||
# CAS Latencies Supported, Third Byte
|
||||
00
|
||||
|
||||
# CAS Latencies Supported, Fourth Byte
|
||||
00
|
||||
|
||||
# Minimum CAS Latency Time (tAAmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Minimum RAS to CAS Delay Time (tRCDmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Minimum RAS to CAS Delay Time (tRPmin) (13.75ns)
|
||||
6E
|
||||
|
||||
# Upper Nibbles for tRASmin and tRCmin (32ns / 45.75ns)
|
||||
11
|
||||
|
||||
# tRASmin, Least Significant Byte (32ns)
|
||||
00
|
||||
|
||||
# tRCmin, Least Significant Byte (45.75ns)
|
||||
6E
|
||||
|
||||
# tRFC1min, LSB (350ns)
|
||||
F0
|
||||
|
||||
# tRFC1min, MSB (350ns)
|
||||
0A
|
||||
|
||||
# tRFC2min, LSB (260ns)
|
||||
20
|
||||
|
||||
# tRFC2min, MSB (260ns)
|
||||
08
|
||||
|
||||
# tRFC4min, LSB (160ns)
|
||||
00
|
||||
|
||||
# tRFC4min, MSB (160ns)
|
||||
05
|
||||
|
||||
# Upper Nibble for tFAW (30ns)
|
||||
00
|
||||
|
||||
# tFAWmin LSB (30ns)
|
||||
F0
|
||||
|
||||
# tRRD_Smin (5.3ns)
|
||||
2B
|
||||
|
||||
# tRRD_L min (6.40ns)
|
||||
34
|
||||
|
||||
# tCCD_Lmin, same bank group (5ns)
|
||||
28
|
||||
|
||||
# tWRmin Upper Nibbles (15ns)
|
||||
00
|
||||
|
||||
# tWRmin (15ns)
|
||||
78
|
||||
|
||||
# tWTRmin Upper Nibbles (2.5ns/7.5ns)
|
||||
00
|
||||
|
||||
# tWTR_Smin (2.5ns)
|
||||
14
|
||||
|
||||
# tWTR_Lmin (7.5ns)
|
||||
3C
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ0-3)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ4-7)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ8-11)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ12-15)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ16-19)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ20-23)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ24-27)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ28-31)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB0-3)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (CB4-7)
|
||||
00
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ32-35)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ36-39)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ40-43)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ44-47)
|
||||
35
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ48-51)
|
||||
16
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ52-55)
|
||||
36
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ56-59)
|
||||
0B
|
||||
|
||||
# Connector to SDRAM Bit Mapping (DQ60-63)
|
||||
35
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00
|
||||
|
||||
# Fine offset for tCCD_Lmin, same bank group (5ns)
|
||||
00
|
||||
|
||||
# tRRD_L min offset (6.40ns)
|
||||
9C
|
||||
|
||||
# tRRD_Smin offset (5.3ns)
|
||||
B5
|
||||
|
||||
# Fine offset for tRCmin (45.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRPmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tRCDmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tAAmin (13.75ns)
|
||||
00
|
||||
|
||||
# Fine offset for tCKAVGmax (1.6ns)
|
||||
E7
|
||||
|
||||
# Fine offset for tCKAVGmin (0.75ns)
|
||||
00
|
||||
|
||||
# CRC for Base Configuration Section, LSB (CRC cover 0~125 byte)
|
||||
FD
|
||||
|
||||
# CRC for Base Configuration Section, MSB (CRC cover 0~125 byte)
|
||||
EE
|
||||
|
||||
# RC Extention, Module Nominal Height (30.00)
|
||||
0F
|
||||
|
||||
# Module Maximum Thickness (1.0/1.2)
|
||||
01
|
||||
|
||||
# Reference Raw Card Used (ZZ0)
|
||||
1F
|
||||
|
||||
# Address Mapping from Edge Connector to DRAM (Standard)
|
||||
00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved (Must be coded as 0x00)
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00
|
||||
|
||||
# CRC for Module Specific Section, LSB (CRC cover 128~253 byte)
|
||||
7D
|
||||
|
||||
# CRC for Module Specific Section, MSB (CRC cover 128~253 byte)
|
||||
21
|
||||
|
||||
# Reserved
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
# Module Manufacturer's ID Code, LSB (SK hynix)
|
||||
80
|
||||
|
||||
# Module Manufacturer's ID Code, MSB (SK hynix)
|
||||
AD
|
||||
|
||||
# Module Manufacturing Location (SK hynix (Icheon))
|
||||
01
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Manufacturing Date (Variable)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Serial Number (Undefined)
|
||||
00
|
||||
|
||||
# Module Part Number (HMAA1GS6CMR6N-VK )
|
||||
48 4D 41 41 31 47 53 36 43 4D 52 36 4E 2D 56 4B
|
||||
20 20 20 20
|
||||
|
||||
# Module Revision Code (Revision 0)
|
||||
00
|
||||
|
||||
# DRAM Manufacturer's ID code, LSB (SK hynix)
|
||||
80
|
||||
|
||||
# DRAM Manufacturer's ID code, MSB (SK hynix)
|
||||
AD
|
||||
|
||||
# DRAM Stepping (Undefined)
|
||||
FF
|
||||
|
||||
# Module Manufacturer's Specific Data
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 DD
|
||||
|
||||
# Reserved
|
||||
00 00
|
||||
|
||||
# End User Programmable
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Micron MT40A1G16KD-062E:E
|
||||
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 7C A0
|
||||
0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47
|
||||
31 36 4B 44 2D 30 36 32 45 3A 45 20 20 31 80 2C
|
||||
45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Micron MT40A1G16KNR-075:E
|
||||
23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00
|
||||
00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 8D 60
|
||||
0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 21 7D
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 31 47
|
||||
31 36 4B 4E 52 2D 30 37 35 3A 45 20 20 31 80 2C
|
||||
45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# MT40A512M16TB-062E:J
|
||||
23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53
|
||||
0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 2C 00 00 00 00 00 00 00 4D 54 34 30 41 35 31
|
||||
32 4D 31 36 54 42 2D 30 36 32 45 3A 4A 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Samsung K4A8G165WC-BCTD
|
||||
23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2e
|
||||
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36
|
||||
35 57 43 2D 42 43 54 44 20 20 20 20 20 00 80 CE
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Samsung K4A8G165WC-BCWE
|
||||
23 11 0C 03 46 21 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98
|
||||
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36
|
||||
35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Samsung K4AAG165WA-BCTD
|
||||
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 F7 4B
|
||||
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36
|
||||
35 57 41 2D 42 43 54 44 20 20 20 20 20 00 80 CE
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Samsung K4AAG165WA-BCWE
|
||||
23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00
|
||||
00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35
|
||||
16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5
|
||||
0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36
|
||||
35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -1,33 +0,0 @@
|
|||
# Samsung K4AAG165WB-MCTD
|
||||
23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00
|
||||
00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A
|
||||
20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04
|
||||
16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E
|
||||
0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B
|
||||
34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
|
@ -44,11 +44,15 @@ endif #($(CONFIG_USE_OEM_BIN),y)
|
|||
# GPIO_NUMBER: FCH GPIO number
|
||||
# GPIO_IO_MUX: Value write to IOMUX to configure this GPIO
|
||||
# GPIO_BANK_CTL: Value write to GPIOBankCtl[23:16] to configure this GPIO
|
||||
# APCB_POPULATE_2ND_CHANNEL: Populates 2nd memory channel in APCB when true.
|
||||
# Trembyle based boards select 1 or 2 channels based on AGPIO84
|
||||
# Dalboz based boards only support 1 channel
|
||||
ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_TREMBYLE),y)
|
||||
APCB_BOARD_ID_GPIO0 = 121 1 0
|
||||
APCB_BOARD_ID_GPIO1 = 120 1 0
|
||||
APCB_BOARD_ID_GPIO2 = 131 3 0
|
||||
APCB_BOARD_ID_GPIO3 = 116 1 0
|
||||
APCB_POPULATE_2ND_CHANNEL = true
|
||||
else ifeq ($(CONFIG_BOARD_GOOGLE_BASEBOARD_DALBOZ),y)
|
||||
APCB_BOARD_ID_GPIO0 = 132 1 0
|
||||
APCB_BOARD_ID_GPIO1 = 90 1 0
|
||||
|
|
|
@ -1,26 +1,13 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
# Ordered List of APCB entries, up to 16.
|
||||
# Entries should match this pattern {NAME}_x{1,2}
|
||||
# There should be a matching SPD hex file in SPD_SOURCES_DIR
|
||||
# matching the pattern {NAME}.spd.hex
|
||||
# The _x{1,2} suffix denotes single or dual channel
|
||||
# Alternatively, generated APCBs stored at
|
||||
# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
|
||||
APCB_SOURCES = samsung-K4A8G165WC-BCTD_x2 # 0b0000
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b0001
|
||||
# b/149596178: We can't use dual channel channel until the PSP supports missing
|
||||
# channels.
|
||||
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010
|
||||
APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x2 # 0b0100
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0101
|
||||
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0110
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b0111
|
||||
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b1000
|
||||
APCB_SOURCES += empty # 0b1001
|
||||
APCB_SOURCES += empty # 0b1010
|
||||
APCB_SOURCES += empty # 0b1011
|
||||
APCB_SOURCES += empty # 0b1100
|
||||
APCB_SOURCES += empty # 0b1101
|
||||
APCB_SOURCES += empty # 0b1110
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = K4A8G165WC-BCTD
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = K4A8G165WC-BCWE
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC
|
||||
SPD_SOURCES += ddr4-spd-6.hex # ID = 4(0b0100) Parts = H5ANAG6NCMR-VKC
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = K4A8G165WC-BCWE
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E
|
||||
SPD_SOURCES += ddr4-spd-2.hex # ID = 7(0b0111) Parts = H5ANAG6NCMR-XNC
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = K4AAG165WA-BCWE
|
||||
|
|
|
@ -0,0 +1,10 @@
|
|||
DRAM Part Name ID to assign
|
||||
K4A8G165WC-BCTD 0 (0000)
|
||||
K4A8G165WC-BCWE 1 (0001)
|
||||
MT40A512M16TB-062E:J 2 (0010)
|
||||
H5AN8G6NDJR-XNC 3 (0011)
|
||||
H5ANAG6NCMR-VKC 4 (0100)
|
||||
K4A8G165WC-BCWE 5 (0101)
|
||||
MT40A1G16KD-062E:E 6 (0110)
|
||||
H5ANAG6NCMR-XNC 7 (0111)
|
||||
K4AAG165WA-BCWE 8 (1000)
|
|
@ -0,0 +1,9 @@
|
|||
K4A8G165WC-BCTD, 0
|
||||
K4A8G165WC-BCWE, 1
|
||||
MT40A512M16TB-062E:J, 2
|
||||
H5AN8G6NDJR-XNC, 3
|
||||
H5ANAG6NCMR-VKC, 4
|
||||
K4A8G165WC-BCWE, 5
|
||||
MT40A1G16KD-062E:E, 6
|
||||
H5ANAG6NCMR-XNC, 7
|
||||
K4AAG165WA-BCWE, 8
|
|
@ -1,25 +1,9 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
# Ordered List of APCB entries, up to 16.
|
||||
# Entries should match this pattern {NAME}_x{1,2}
|
||||
# There should be a matching SPD hex file in SPD_SOURCES_DIR
|
||||
# matching the pattern {NAME}.spd.hex
|
||||
# The _x{1,2} suffix denotes single or dual channel
|
||||
# Alternatively, generated APCBs stored at
|
||||
# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
|
||||
APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1 # 0b0010
|
||||
APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1 # 0b0011
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100
|
||||
APCB_SOURCES += empty # 0b0101
|
||||
APCB_SOURCES += empty # 0b0110
|
||||
APCB_SOURCES += empty # 0b0111
|
||||
APCB_SOURCES += empty # 0b1000
|
||||
APCB_SOURCES += empty # 0b1001
|
||||
APCB_SOURCES += empty # 0b1010
|
||||
APCB_SOURCES += empty # 0b1011
|
||||
APCB_SOURCES += empty # 0b1100
|
||||
APCB_SOURCES += empty # 0b1101
|
||||
APCB_SOURCES += empty # 0b1110
|
||||
APCB_SOURCES += empty # 0b1111
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = HMA851S6CJR6N-VK
|
||||
SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD
|
||||
SPD_SOURCES += ddr4-spd-5.hex # ID = 3(0b0011) Parts = K4AAG165WB-MCTD
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE
|
||||
|
|
|
@ -0,0 +1,6 @@
|
|||
DRAM Part Name ID to assign
|
||||
HMA851S6CJR6N-VK 0 (0000)
|
||||
H5ANAG6NCMR-VKC 1 (0001)
|
||||
K4A8G165WC-BCTD 2 (0010)
|
||||
K4AAG165WB-MCTD 3 (0011)
|
||||
K4A8G165WC-BCWE 4 (0100)
|
|
@ -0,0 +1,5 @@
|
|||
HMA851S6CJR6N-VK, 0
|
||||
H5ANAG6NCMR-VKC, 1
|
||||
K4A8G165WC-BCTD, 2
|
||||
K4AAG165WB-MCTD, 3
|
||||
K4A8G165WC-BCWE, 4
|
|
@ -1,25 +1,15 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
# Ordered List of APCB entries, up to 16.
|
||||
# Entries should match this pattern {NAME}_x{1,2}
|
||||
# There should be a matching SPD hex file in SPD_SOURCES_DIR
|
||||
# matching the pattern {NAME}.spd.hex
|
||||
# The _x{1,2} suffix denotes single or dual channel
|
||||
# Alternatively, generated APCBs stored at
|
||||
# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
|
||||
APCB_SOURCES = hynix-HMA851S6CJR6N-VK_x1 # 0b0000
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCTD_x1 # 0b0010
|
||||
APCB_SOURCES += samsung-K4AAG165WB-MCTD_x1 # 0b0011
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100
|
||||
APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0101
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x1 # 0b0110
|
||||
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0111
|
||||
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b1000
|
||||
APCB_SOURCES += samsung-K4AAG165WA-BCTD_x1 # 0b1001
|
||||
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b1010
|
||||
APCB_SOURCES += empty # 0b1011
|
||||
APCB_SOURCES += empty # 0b1100
|
||||
APCB_SOURCES += empty # 0b1101
|
||||
APCB_SOURCES += empty # 0b1110
|
||||
APCB_SOURCES += empty # 0b1111
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = HMA851S6CJR6N-VK
|
||||
SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD
|
||||
SPD_SOURCES += ddr4-spd-5.hex # ID = 3(0b0011) Parts = K4AAG165WB-MCTD
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC
|
||||
SPD_SOURCES += ddr4-spd-2.hex # ID = 6(0b0110) Parts = H5ANAG6NCMR-XNC
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 7(0b0111) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 8(0b1000) Parts = MT40A1G16KD-062E:E
|
||||
SPD_SOURCES += ddr4-spd-8.hex # ID = 9(0b1001) Parts = K4AAG165WA-BCTD
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = K4AAG165WA-BCWE
|
||||
|
|
|
@ -0,0 +1,12 @@
|
|||
DRAM Part Name ID to assign
|
||||
HMA851S6CJR6N-VK 0 (0000)
|
||||
H5ANAG6NCMR-VKC 1 (0001)
|
||||
K4A8G165WC-BCTD 2 (0010)
|
||||
K4AAG165WB-MCTD 3 (0011)
|
||||
K4A8G165WC-BCWE 4 (0100)
|
||||
H5AN8G6NDJR-XNC 5 (0101)
|
||||
H5ANAG6NCMR-XNC 6 (0110)
|
||||
MT40A512M16TB-062E:J 7 (0111)
|
||||
MT40A1G16KD-062E:E 8 (1000)
|
||||
K4AAG165WA-BCTD 9 (1001)
|
||||
K4AAG165WA-BCWE 10 (1010)
|
|
@ -0,0 +1,11 @@
|
|||
HMA851S6CJR6N-VK, 0
|
||||
H5ANAG6NCMR-VKC, 1
|
||||
K4A8G165WC-BCTD, 2
|
||||
K4AAG165WB-MCTD, 3
|
||||
K4A8G165WC-BCWE, 4
|
||||
H5AN8G6NDJR-XNC, 5
|
||||
H5ANAG6NCMR-XNC, 6
|
||||
MT40A512M16TB-062E:J, 7
|
||||
MT40A1G16KD-062E:E, 8
|
||||
K4AAG165WA-BCTD, 9
|
||||
K4AAG165WA-BCWE, 10
|
|
@ -1,25 +1,9 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
# Ordered List of APCB entries, up to 16.
|
||||
# Entries should match this pattern {NAME}_x{1,2}
|
||||
# There should be a matching SPD hex file in SPD_SOURCES_DIR
|
||||
# matching the pattern {NAME}.spd.hex
|
||||
# The _x{1,2} suffix denotes single or dual channel
|
||||
# Alternatively, generated APCBs stored at
|
||||
# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
|
||||
APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x2 # 0b0000
|
||||
APCB_SOURCES += hynix-HMAA1GS6CMR6N-VK_x2 # 0b0001
|
||||
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b0010
|
||||
APCB_SOURCES += micron-MT40A1G16KNR-075-E_x2 # 0b0011
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCTD_x2 # 0b0100
|
||||
APCB_SOURCES += empty # 0b0101
|
||||
APCB_SOURCES += empty # 0b0110
|
||||
APCB_SOURCES += empty # 0b0111
|
||||
APCB_SOURCES += empty # 0b1000
|
||||
APCB_SOURCES += empty # 0b1001
|
||||
APCB_SOURCES += empty # 0b1010
|
||||
APCB_SOURCES += empty # 0b1011
|
||||
APCB_SOURCES += empty # 0b1100
|
||||
APCB_SOURCES += empty # 0b1101
|
||||
APCB_SOURCES += empty # 0b1110
|
||||
APCB_SOURCES += empty # 0b1111
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC
|
||||
SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001)
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-4.hex # ID = 3(0b0011) Parts = MT40A1G16KNR-075:E
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCTD
|
||||
|
|
|
@ -0,0 +1,5 @@
|
|||
DRAM Part Name ID to assign
|
||||
H5AN8G6NCJR-VKC 0 (0000)
|
||||
MT40A512M16TB-062E:J 2 (0010)
|
||||
MT40A1G16KNR-075:E 3 (0011)
|
||||
K4A8G165WC-BCTD 4 (0100)
|
|
@ -0,0 +1,4 @@
|
|||
H5AN8G6NCJR-VKC,0
|
||||
MT40A512M16TB-062E:J,2
|
||||
MT40A1G16KNR-075:E, 3
|
||||
K4A8G165WC-BCTD,4
|
|
@ -1,26 +1,14 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
# Ordered List of APCB entries, up to 16.
|
||||
# Entries should match this pattern {NAME}_x{1,2}
|
||||
# There should be a matching SPD hex file in SPD_SOURCES_DIR
|
||||
# matching the pattern {NAME}.spd.hex
|
||||
# The _x{1,2} suffix denotes single or dual channel
|
||||
# Alternatively, generated APCBs stored at
|
||||
# 3rdparty/blobs/mainboard/$(MAINBOARDDIR)/APCB_{NAME}.bin will be included.
|
||||
APCB_SOURCES = samsung-K4AAG165WA-BCWE_x2 # 0b0000
|
||||
APCB_SOURCES += empty # 0b0001
|
||||
# b/149596178: We can't use dual channel channel until the PSP supports missing
|
||||
# channels.
|
||||
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0010
|
||||
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b0011
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0100
|
||||
APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0101
|
||||
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0110
|
||||
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b0111
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-XNC_x2 # 0b1000
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x2 # 0b1001
|
||||
APCB_SOURCES += empty # 0b1010
|
||||
APCB_SOURCES += empty # 0b1011
|
||||
APCB_SOURCES += empty # 0b1100
|
||||
APCB_SOURCES += empty # 0b1101
|
||||
APCB_SOURCES += empty # 0b1110
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 0(0b0000) Parts = K4AAG165WA-BCWE
|
||||
SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001)
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = MT40A1G16KD-062E:E
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = K4A8G165WC-BCWE
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 5(0b0101) Parts = H5AN8G6NDJR-XNC
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 6(0b0110) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 7(0b0111) Parts = K4AAG165WA-BCWE
|
||||
SPD_SOURCES += ddr4-spd-2.hex # ID = 8(0b1000) Parts = H5ANAG6NCMR-XNC
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 9(0b1001) Parts = K4A8G165WC-BCWE
|
||||
|
|
|
@ -0,0 +1,10 @@
|
|||
DRAM Part Name ID to assign
|
||||
K4AAG165WA-BCWE 0 (0000)
|
||||
MT40A512M16TB-062E:J 2 (0010)
|
||||
MT40A1G16KD-062E:E 3 (0011)
|
||||
K4A8G165WC-BCWE 4 (0100)
|
||||
H5AN8G6NDJR-XNC 5 (0101)
|
||||
MT40A512M16TB-062E:J 6 (0110)
|
||||
K4AAG165WA-BCWE 7 (0111)
|
||||
H5ANAG6NCMR-XNC 8 (1000)
|
||||
K4A8G165WC-BCWE 9 (1001)
|
|
@ -0,0 +1,9 @@
|
|||
K4AAG165WA-BCWE, 0
|
||||
MT40A512M16TB-062E:J, 2
|
||||
MT40A1G16KD-062E:E, 3
|
||||
K4A8G165WC-BCWE, 4
|
||||
H5AN8G6NDJR-XNC, 5
|
||||
MT40A512M16TB-062E:J, 6
|
||||
K4AAG165WA-BCWE, 7
|
||||
H5ANAG6NCMR-XNC, 8
|
||||
K4A8G165WC-BCWE, 9
|
|
@ -1,5 +1,5 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
subdirs-y += ../baseboard/spd
|
||||
subdirs-y += ../spd
|
||||
|
||||
ramstage-y += gpio.c
|
||||
|
|
|
@ -0,0 +1,6 @@
|
|||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC
|
||||
SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC
|
|
@ -0,0 +1,3 @@
|
|||
DRAM Part Name ID to assign
|
||||
H5AN8G6NCJR-VKC 0 (0000)
|
||||
H5ANAG6NCMR-VKC 1 (0001)
|
|
@ -0,0 +1,2 @@
|
|||
H5AN8G6NCJR-VKC, 0
|
||||
H5ANAG6NCMR-VKC, 1
|
|
@ -1,26 +1,11 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
# Ordered List of APCB entries, up to 16.
|
||||
# Entries should match this pattern {NAME}_x{1,2}
|
||||
# There should be a matching SPD hex file in SPD_SOURCES_DIR
|
||||
# matching the pattern {NAME}.spd.hex
|
||||
# The _x{1,2} suffix denotes single or dual channel
|
||||
# TODO: Remove channel suffix when b:141434940 is fixed
|
||||
# Alternatively, generated APCBs stored at
|
||||
# CONFIG_APCB_BLOB_DIR/APCB_{NAME}.bin can be included.
|
||||
APCB_SOURCES = hynix-H5AN8G6NCJR-VKC_x1 # 0b0000
|
||||
APCB_SOURCES += hynix-H5ANAG6NCMR-VKC_x1 # 0b0001
|
||||
APCB_SOURCES += samsung-K4A8G165WC-BCWE_x1 # 0b0010
|
||||
APCB_SOURCES += hynix-H5AN8G6NDJR-XNC_x1 # 0b0011
|
||||
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x1 # 0b0100
|
||||
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b0101
|
||||
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b0110
|
||||
APCB_SOURCES += empty # 0b0111
|
||||
APCB_SOURCES += empty # 0b1000
|
||||
APCB_SOURCES += empty # 0b1001
|
||||
APCB_SOURCES += empty # 0b1010
|
||||
APCB_SOURCES += empty # 0b1011
|
||||
APCB_SOURCES += empty # 0b1100
|
||||
APCB_SOURCES += empty # 0b1101
|
||||
APCB_SOURCES += empty # 0b1110
|
||||
APCB_SOURCES += empty # 0b1111
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-3.hex # ID = 0(0b0000) Parts = H5AN8G6NCJR-VKC
|
||||
SPD_SOURCES += ddr4-spd-6.hex # ID = 1(0b0001) Parts = H5ANAG6NCMR-VKC
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCWE
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 3(0b0011) Parts = H5AN8G6NDJR-XNC
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 4(0b0100) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 5(0b0101) Parts = K4AAG165WA-BCWE
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 6(0b0110) Parts = MT40A1G16KD-062E:E
|
||||
|
|
|
@ -0,0 +1,8 @@
|
|||
DRAM Part Name ID to assign
|
||||
H5AN8G6NCJR-VKC 0 (0000)
|
||||
H5ANAG6NCMR-VKC 1 (0001)
|
||||
K4A8G165WC-BCWE 2 (0010)
|
||||
H5AN8G6NDJR-XNC 3 (0011)
|
||||
MT40A512M16TB-062E:J 4 (0100)
|
||||
K4AAG165WA-BCWE 5 (0101)
|
||||
MT40A1G16KD-062E:E 6 (0110)
|
|
@ -0,0 +1,7 @@
|
|||
H5AN8G6NCJR-VKC, 0
|
||||
H5ANAG6NCMR-VKC, 1
|
||||
K4A8G165WC-BCWE, 2
|
||||
H5AN8G6NDJR-XNC, 3
|
||||
MT40A512M16TB-062E:J, 4
|
||||
K4AAG165WA-BCWE, 5
|
||||
MT40A1G16KD-062E:E, 6
|
|
@ -1,18 +1,16 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
## This is an auto-generated file. Do not edit!!
|
||||
|
||||
APCB_SOURCES = micron-MT40A512M16TB-062E-J_x1 # 0b00000
|
||||
APCB_SOURCES += hynix-H5AN8G6NCJR-XNC_x1 # 0b00001
|
||||
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x1 # 0b00010
|
||||
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x1 # 0b00011
|
||||
APCB_SOURCES += empty # 0b00100
|
||||
APCB_SOURCES += empty # 0b00101
|
||||
APCB_SOURCES += empty # 0b00110
|
||||
APCB_SOURCES += empty # 0b00111
|
||||
APCB_SOURCES += micron-MT40A512M16TB-062E-J_x2 # 0b01000
|
||||
APCB_SOURCES += hynix-H5AN8G6NCJR-XNC_x2 # 0b01001
|
||||
APCB_SOURCES += micron-MT40A1G16KD-062E-E_x2 # 0b01010
|
||||
APCB_SOURCES += samsung-K4AAG165WA-BCWE_x2 # 0b01011
|
||||
APCB_SOURCES += empty # 0b01100
|
||||
APCB_SOURCES += empty # 0b01101
|
||||
APCB_SOURCES += empty # 0b01110
|
||||
APCB_SOURCES += empty # 0b01111
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 0(0b0000) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 1(0b0001) Parts = H5AN8G6NCJR-XNC
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 2(0b0010) Parts = MT40A1G16KD-062E:E
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 3(0b0011) Parts = K4AAG165WA-BCWE
|
||||
SPD_SOURCES += ddr4-spd-empty.hex # ID = 4(0b0100)
|
||||
SPD_SOURCES += ddr4-spd-empty.hex # ID = 5(0b0101)
|
||||
SPD_SOURCES += ddr4-spd-empty.hex # ID = 6(0b0110)
|
||||
SPD_SOURCES += ddr4-spd-empty.hex # ID = 7(0b0111)
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 8(0b1000) Parts = MT40A512M16TB-062E:J
|
||||
SPD_SOURCES += ddr4-spd-1.hex # ID = 9(0b1001) Parts = H5AN8G6NCJR-XNC
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 10(0b1010) Parts = MT40A1G16KD-062E:E
|
||||
SPD_SOURCES += ddr4-spd-7.hex # ID = 11(0b1011) Parts = K4AAG165WA-BCWE
|
||||
|
|
|
@ -0,0 +1,9 @@
|
|||
DRAM Part Name ID to assign
|
||||
MT40A512M16TB-062E:J 0 (0000)
|
||||
H5AN8G6NCJR-XNC 1 (0001)
|
||||
MT40A1G16KD-062E:E 2 (0010)
|
||||
K4AAG165WA-BCWE 3 (0011)
|
||||
MT40A512M16TB-062E:J 8 (1000)
|
||||
H5AN8G6NCJR-XNC 9 (1001)
|
||||
MT40A1G16KD-062E:E 10 (1010)
|
||||
K4AAG165WA-BCWE 11 (1011)
|
|
@ -0,0 +1,8 @@
|
|||
MT40A512M16TB-062E:J, 0
|
||||
H5AN8G6NCJR-XNC, 1
|
||||
MT40A1G16KD-062E:E, 2
|
||||
K4AAG165WA-BCWE, 3
|
||||
MT40A512M16TB-062E:J, 8
|
||||
H5AN8G6NCJR-XNC, 9
|
||||
MT40A1G16KD-062E:E, 10
|
||||
K4AAG165WA-BCWE, 11
|
|
@ -198,7 +198,7 @@ endif
|
|||
#
|
||||
|
||||
# type = 0x60
|
||||
PSP_APCB_FILES=$(foreach f, $(APCB_SOURCES), $(obj)/APCB_$(f).bin)
|
||||
PSP_APCB_FILES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).bin)
|
||||
|
||||
# type = 0x61
|
||||
PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
|
||||
|
@ -390,16 +390,7 @@ $(obj)/APCB_%.bin: $(MAINBOARD_BLOBS_DIR)/APCB_%.bin
|
|||
# APCB binary with magic numbers to be replaced by apcb_edit tool
|
||||
APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin
|
||||
|
||||
$(obj)/APCB_empty.bin: $(APCB_MAGIC_BLOB) $(APCB_EDIT_TOOL)
|
||||
$(APCB_EDIT_TOOL) \
|
||||
$(APCB_MAGIC_BLOB) \
|
||||
$@ \
|
||||
--board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \
|
||||
--board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \
|
||||
--board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \
|
||||
--board_id_gpio3 $(APCB_BOARD_ID_GPIO3)
|
||||
|
||||
$(obj)/APCB_%_x1.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \
|
||||
$(obj)/APCB_%.bin: $$(SPD_SOURCES_DIR)/%.hex \
|
||||
$(APCB_EDIT_TOOL) \
|
||||
$(APCB_MAGIC_BLOB)
|
||||
$(APCB_EDIT_TOOL) \
|
||||
|
@ -408,21 +399,7 @@ $(obj)/APCB_%_x1.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \
|
|||
--hex \
|
||||
--strip_manufacturer_information \
|
||||
--spd_0_0 $< \
|
||||
--board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \
|
||||
--board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \
|
||||
--board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \
|
||||
--board_id_gpio3 $(APCB_BOARD_ID_GPIO3)
|
||||
|
||||
$(obj)/APCB_%_x2.bin: $$(SPD_SOURCES_DIR)/%.spd.hex \
|
||||
$(APCB_EDIT_TOOL) \
|
||||
$(APCB_MAGIC_BLOB)
|
||||
$(APCB_EDIT_TOOL) \
|
||||
$(APCB_MAGIC_BLOB) \
|
||||
$@ \
|
||||
--hex \
|
||||
--strip_manufacturer_information \
|
||||
--spd_0_0 $< \
|
||||
--spd_1_0 $< \
|
||||
$(if $(APCB_POPULATE_2ND_CHANNEL), --spd_1_0 $<, ) \
|
||||
--board_id_gpio0 $(APCB_BOARD_ID_GPIO0) \
|
||||
--board_id_gpio1 $(APCB_BOARD_ID_GPIO1) \
|
||||
--board_id_gpio2 $(APCB_BOARD_ID_GPIO2) \
|
||||
|
|
Loading…
Reference in New Issue