lynxpoint: Add power management helper functions
There are subtle yet significant differences in some of the registers in the power management region between LynxPoint-H and LynxPoint-LP. In order to reduce code that is accessing these registers and would need special cases this adds a number of helper functions that can be used in both ramstage and SMM. This commit just adds the new functions, subsequent commits will start to use them. Change-Id: I411da75da519f5b3198a408078cbf3114e426992 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2813 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Duncan Laurie
Ronald G. Minnich
parent
1ad5564dd6
commit
55cdf55190
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@ -44,8 +44,9 @@ ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
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romstage-$(CONFIG_USBDEBUG) += usb_debug.c
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@ -28,8 +28,6 @@
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#define GPIO_SER_BLINK_CS 0x20
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#define GPIO_SER_BLINK_DATA 0x24
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#define GPIO_ROUTE(set) (0x30 + ((set) * 4))
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#define GPIO_ALT_GPI_SMI_STS 0x50
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#define GPIO_ALT_GPI_SMI_EN 0x54
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#define GPIO_RESET(set) (0x60 + ((set) * 4))
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#define GPIO_GLOBAL_CONFIG 0x7c
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#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4))
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@ -132,6 +132,32 @@ int pch_silicon_type(void);
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int pch_is_lp(void);
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u16 get_pmbase(void);
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u16 get_gpiobase(void);
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/* Power Management register handling in pmutil.c */
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/* PM1_CNT */
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void enable_pm1_control(u32 mask);
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void disable_pm1_control(u32 mask);
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/* PM1 */
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u16 clear_pm1_status(void);
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void enable_pm1(u32 mask);
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u32 clear_smi_status(void);
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/* SMI */
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void enable_smi(u32 mask);
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void disable_smi(u32 mask);
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/* ALT_GP_SMI */
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u32 clear_alt_smi_status(void);
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void enable_alt_smi(u32 mask);
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/* TCO */
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u32 clear_tco_status(void);
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void enable_tco_sci(void);
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/* GPE0 */
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u32 clear_gpe_status(void);
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void clear_gpe_enable(void);
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void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4);
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void disable_all_gpe(void);
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void enable_gpe(u32 mask);
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void disable_gpe(u32 mask);
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#if !defined(__PRE_RAM__) && !defined(__SMM__)
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#include <device/device.h>
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#include <arch/acpi.h>
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@ -590,10 +616,12 @@ unsigned get_gpios(const int *gpio_num_array);
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_STS_2 0x24
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#define GPE0_EN 0x28
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#define PME_B0_EN (1 << 13)
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#define PME_EN (1 << 11)
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#define TCOSCI_EN (1 << 6)
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#define GPE0_EN_2 0x2c
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#define SMI_EN 0x30
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#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic
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#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
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@ -618,6 +646,18 @@ unsigned get_gpios(const int *gpio_num_array);
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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#define ALT_GP_SMI_EN2 0x5c
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#define ALT_GP_SMI_STS2 0x5e
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/* Lynxpoint LP */
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#define LP_GPE0_STS_1 0x80 /* GPIO 0-31 */
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#define LP_GPE0_STS_2 0x84 /* GPIO 32-63 */
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#define LP_GPE0_STS_3 0x88 /* GPIO 64-94 */
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#define LP_GPE0_STS_4 0x8c /* Standard GPE */
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#define LP_GPE0_EN_1 0x90
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#define LP_GPE0_EN_2 0x94
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#define LP_GPE0_EN_3 0x98
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#define LP_GPE0_EN_4 0x9c
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/*
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* SPI Opcode Menu setup for SPIBAR lockdown
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@ -0,0 +1,567 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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/*
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* Helper functions for dealing with power management registers
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* and the differences between LynxPoint-H and LynxPoint-LP.
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*/
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#include <arch/io.h>
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#ifdef __SMM__
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#include <arch/romcc_io.h>
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#include <device/pci_def.h>
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#else /* !__SMM__ */
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#include <device/device.h>
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#include <device/pci.h>
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#endif
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#include <console/console.h>
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#include "pch.h"
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#if CONFIG_INTEL_LYNXPOINT_LP
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#include "lp_gpio.h"
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#endif
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/* These defines are here to handle the LP variant code dynamically. If these
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* values are defined in lp_gpio.h but when a non-LP board is being built, the
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* build will fail. */
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#define GPIO_ALT_GPI_SMI_STS 0x50
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#define GPIO_ALT_GPI_SMI_EN 0x54
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/* Print status bits with descriptive names */
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static void print_status_bits(u32 status, const char *bit_names[])
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{
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int i;
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if (!status)
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return;
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for (i=31; i>=0; i--) {
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if (status & (1 << i)) {
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if (bit_names[i])
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printk(BIOS_DEBUG, "%s ", bit_names[i]);
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else
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printk(BIOS_DEBUG, "BIT%d ", i);
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}
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}
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}
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/* Print status bits as GPIO numbers */
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static void print_gpio_status(u32 status, int start)
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{
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int i;
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if (!status)
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return;
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for (i=31; i>=0; i--) {
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if (status & (1 << i))
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printk(BIOS_DEBUG, "GPIO%d ", start + i);
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}
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}
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/*
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* PM1_CNT
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*/
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/* Enable events in PM1 control register */
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void enable_pm1_control(u32 mask)
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{
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u32 pm1_cnt = inl(get_pmbase() + PM1_CNT);
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pm1_cnt |= mask;
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outl(pm1_cnt, get_pmbase() + PM1_CNT);
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}
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/* Disable events in PM1 control register */
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void disable_pm1_control(u32 mask)
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{
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u32 pm1_cnt = inl(get_pmbase() + PM1_CNT);
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pm1_cnt &= ~mask;
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outl(pm1_cnt, get_pmbase() + PM1_CNT);
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}
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/*
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* PM1
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*/
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/* Clear and return PM1 status register */
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static u16 reset_pm1_status(void)
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{
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u16 pm1_sts = inw(get_pmbase() + PM1_STS);
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outw(pm1_sts, get_pmbase() + PM1_STS);
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return pm1_sts;
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}
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/* Print PM1 status bits */
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static u16 print_pm1_status(u16 pm1_sts)
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{
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const char *pm1_sts_bits[] = {
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[0] = "TMROF",
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[4] = "BM",
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[5] = "GBL",
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[8] = "PWRBTN",
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[10] = "RTC",
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[11] = "PRBTNOR",
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[14] = "PCIEXPWAK",
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[15] = "WAK",
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};
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if (!pm1_sts)
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return 0;
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printk(BIOS_SPEW, "PM1_STS: ");
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print_status_bits(pm1_sts, pm1_sts_bits);
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printk(BIOS_SPEW, "\n");
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return pm1_sts;
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}
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/* Print, clear, and return PM1 status */
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u16 clear_pm1_status(void)
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{
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return print_pm1_status(reset_pm1_status());
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}
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/* Enable PM1 event */
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void enable_pm1(u32 mask)
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{
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u32 pm1_en = inl(get_pmbase() + PM1_EN);
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pm1_en |= mask;
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outl(pm1_en, get_pmbase() + PM1_EN);
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}
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/*
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* SMI
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*/
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/* Clear and return SMI status register */
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static u32 reset_smi_status(void)
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{
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u32 smi_sts = inl(get_pmbase() + SMI_STS);
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outl(smi_sts, get_pmbase() + SMI_STS);
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return smi_sts;
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}
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/* Print SMI status bits */
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static u32 print_smi_status(u32 smi_sts)
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{
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const char *smi_sts_bits[] = {
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[2] = "BIOS",
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[3] = "LEGACY_USB",
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[4] = "SLP_SMI",
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[5] = "APM",
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[6] = "SWSMI_TMR",
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[8] = "PM1",
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[9] = "GPE0",
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[10] = "GPI",
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[11] = "MCSMI",
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[12] = "DEVMON",
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[13] = "TCO",
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[14] = "PERIODIC",
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[15] = "SERIRQ_SMI",
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[16] = "SMBUS_SMI",
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[17] = "LEGACY_USB2",
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[18] = "INTEL_USB2",
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[20] = "PCI_EXP_SMI",
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[21] = "MONITOR",
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[26] = "SPI",
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[27] = "GPIO_UNLOCK"
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};
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if (!smi_sts)
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return 0;
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printk(BIOS_DEBUG, "SMI_STS: ");
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print_status_bits(smi_sts, smi_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return smi_sts;
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}
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/* Print, clear, and return SMI status */
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u32 clear_smi_status(void)
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{
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return print_smi_status(reset_smi_status());
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}
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/* Enable SMI event */
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void enable_smi(u32 mask)
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{
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u32 smi_en = inl(get_pmbase() + SMI_EN);
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smi_en |= mask;
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outl(smi_en, get_pmbase() + SMI_EN);
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}
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/* Disable SMI event */
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void disable_smi(u32 mask)
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{
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u32 smi_en = inl(get_pmbase() + SMI_EN);
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smi_en &= ~mask;
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outl(smi_en, get_pmbase() + SMI_EN);
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}
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/*
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* ALT_GP_SMI
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*/
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/* Clear GPIO SMI status and return events that are enabled and active */
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static u32 reset_alt_smi_status(void)
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{
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u32 alt_sts, alt_en;
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if (pch_is_lp()) {
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/* LynxPoint-LP moves this to GPIO region as dword */
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alt_sts = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_STS);
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outl(alt_sts, get_gpiobase() + GPIO_ALT_GPI_SMI_STS);
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alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN);
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} else {
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u16 pmbase = get_pmbase();
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/* LynxPoint-H adds a second enable/status word */
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alt_sts = inw(pmbase + ALT_GP_SMI_STS2);
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outw(alt_sts & 0xffff, pmbase + ALT_GP_SMI_STS2);
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alt_sts <<= 16;
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alt_sts |= inw(pmbase + ALT_GP_SMI_STS);
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outw(alt_sts & 0xffff, pmbase + ALT_GP_SMI_STS);
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alt_en = inw(pmbase + ALT_GP_SMI_EN2);
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alt_en <<= 16;
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alt_en |= inw(pmbase + ALT_GP_SMI_EN);
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}
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/* Only report enabled events */
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return alt_sts & alt_en;
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}
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/* Print GPIO SMI status bits */
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static u32 print_alt_smi_status(u32 alt_sts)
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{
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if (!alt_sts)
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return 0;
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printk(BIOS_DEBUG, "ALT_STS: ");
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if (pch_is_lp()) {
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/* First 16 events are GPIO 32-47 */
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print_gpio_status(alt_sts & 0xffff, 32);
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} else {
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const char *alt_sts_bits_high[] = {
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[0] = "GPIO17",
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[1] = "GPIO19",
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[2] = "GPIO21",
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[3] = "GPIO22",
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[4] = "GPIO43",
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[5] = "GPIO56",
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[6] = "GPIO57",
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[7] = "GPIO60",
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};
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/* First 16 events are GPIO 0-15 */
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print_gpio_status(alt_sts & 0xffff, 0);
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print_status_bits(alt_sts >> 16, alt_sts_bits_high);
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}
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printk(BIOS_DEBUG, "\n");
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return alt_sts;
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}
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/* Print, clear, and return GPIO SMI status */
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u32 clear_alt_smi_status(void)
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{
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return print_alt_smi_status(reset_alt_smi_status());
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}
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/* Enable GPIO SMI events */
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void enable_alt_smi(u32 mask)
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{
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if (pch_is_lp()) {
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u32 alt_en;
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alt_en = inl(get_gpiobase() + GPIO_ALT_GPI_SMI_EN);
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alt_en |= mask;
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outl(alt_en, get_gpiobase() + GPIO_ALT_GPI_SMI_EN);
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} else {
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u16 pmbase = get_pmbase();
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u16 alt_en;
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/* Lower enable register */
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alt_en = inw(pmbase + ALT_GP_SMI_EN);
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alt_en |= mask & 0xffff;
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outw(alt_en, pmbase + ALT_GP_SMI_EN);
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/* Upper enable register */
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alt_en = inw(pmbase + ALT_GP_SMI_EN2);
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alt_en |= (mask >> 16) & 0xffff;
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outw(alt_en, pmbase + ALT_GP_SMI_EN2);
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}
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}
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/*
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* TCO
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*/
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/* Clear TCO status and return events that are enabled and active */
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static u32 reset_tco_status(void)
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{
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u32 tcobase = get_pmbase() + 0x60;
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u32 tco_sts = inl(tcobase + 0x04);
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u32 tco_en = inl(get_pmbase() + 0x68);
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/* Don't clear BOOT_STS before SECOND_TO_STS */
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outl(tco_sts & ~(1 << 18), tcobase + 0x04);
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/* Clear BOOT_STS */
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if (tco_sts & (1 << 18))
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outl(tco_sts & (1 << 18), tcobase + 0x04);
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return tco_sts & tco_en;
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}
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/* Print TCO status bits */
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static u32 print_tco_status(u32 tco_sts)
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{
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const char *tco_sts_bits[] = {
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[0] = "NMI2SMI",
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[1] = "SW_TCO",
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[2] = "TCO_INT",
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[3] = "TIMEOUT",
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[7] = "NEWCENTURY",
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[8] = "BIOSWR",
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[9] = "DMISCI",
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[10] = "DMISMI",
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[12] = "DMISERR",
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[13] = "SLVSEL",
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[16] = "INTRD_DET",
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[17] = "SECOND_TO",
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[18] = "BOOT",
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[20] = "SMLINK_SLV"
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};
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if (!tco_sts)
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return 0;
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printk(BIOS_DEBUG, "TCO_STS: ");
|
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print_status_bits(tco_sts, tco_sts_bits);
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
return tco_sts;
|
||||
}
|
||||
|
||||
/* Print, clear, and return TCO status */
|
||||
u32 clear_tco_status(void)
|
||||
{
|
||||
return print_tco_status(reset_tco_status());
|
||||
}
|
||||
|
||||
/* Enable TCO SCI */
|
||||
void enable_tco_sci(void)
|
||||
{
|
||||
u16 gpe0_sts = pch_is_lp() ? LP_GPE0_STS_4 : GPE0_STS;
|
||||
|
||||
/* Clear pending events */
|
||||
outl(get_pmbase() + gpe0_sts, TCOSCI_STS);
|
||||
|
||||
/* Enable TCO SCI events */
|
||||
enable_gpe(TCOSCI_EN);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* GPE0
|
||||
*/
|
||||
|
||||
/* Clear a GPE0 status and return events that are enabled and active */
|
||||
static u32 reset_gpe_status(u16 sts_reg, u16 en_reg)
|
||||
{
|
||||
u32 gpe0_sts = inl(get_pmbase() + sts_reg);
|
||||
u32 gpe0_en = inl(get_pmbase() + en_reg);
|
||||
|
||||
outl(gpe0_sts, get_pmbase() + sts_reg);
|
||||
|
||||
/* Only report enabled events */
|
||||
return gpe0_sts & gpe0_en;
|
||||
}
|
||||
|
||||
/* Print GPE0 status bits */
|
||||
static u32 print_gpe_status(u32 gpe0_sts, const char *bit_names[])
|
||||
{
|
||||
if (!gpe0_sts)
|
||||
return 0;
|
||||
|
||||
printk(BIOS_DEBUG, "GPE0_STS: ");
|
||||
print_status_bits(gpe0_sts, bit_names);
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
return gpe0_sts;
|
||||
}
|
||||
|
||||
/* Print GPE0 GPIO status bits */
|
||||
static u32 print_gpe_gpio(u32 gpe0_sts, int start)
|
||||
{
|
||||
if (!gpe0_sts)
|
||||
return 0;
|
||||
|
||||
printk(BIOS_DEBUG, "GPE0_STS: ");
|
||||
print_gpio_status(gpe0_sts, start);
|
||||
printk(BIOS_DEBUG, "\n");
|
||||
|
||||
return gpe0_sts;
|
||||
}
|
||||
|
||||
/* Print, clear, and return LynxPoint-H GPE0 status */
|
||||
static u32 clear_lpt_gpe_status(void)
|
||||
{
|
||||
const char *gpe0_sts_bits_low[] = {
|
||||
[1] = "HOTPLUG",
|
||||
[2] = "SWGPE",
|
||||
[6] = "TCO_SCI",
|
||||
[7] = "SMB_WAK",
|
||||
[8] = "RI",
|
||||
[9] = "PCI_EXP",
|
||||
[10] = "BATLOW",
|
||||
[11] = "PME",
|
||||
[13] = "PME_B0",
|
||||
[16] = "GPIO0",
|
||||
[17] = "GPIO1",
|
||||
[18] = "GPIO2",
|
||||
[19] = "GPIO3",
|
||||
[20] = "GPIO4",
|
||||
[21] = "GPIO5",
|
||||
[22] = "GPIO6",
|
||||
[23] = "GPIO7",
|
||||
[24] = "GPIO8",
|
||||
[25] = "GPIO9",
|
||||
[26] = "GPIO10",
|
||||
[27] = "GPIO11",
|
||||
[28] = "GPIO12",
|
||||
[29] = "GPIO13",
|
||||
[30] = "GPIO14",
|
||||
[31] = "GPIO15",
|
||||
};
|
||||
const char *gpe0_sts_bits_high[] = {
|
||||
[3] = "GPIO27",
|
||||
[6] = "WADT",
|
||||
[24] = "GPIO17",
|
||||
[25] = "GPIO19",
|
||||
[26] = "GPIO21",
|
||||
[27] = "GPIO22",
|
||||
[28] = "GPIO43",
|
||||
[29] = "GPIO56",
|
||||
[30] = "GPIO57",
|
||||
[31] = "GPIO60",
|
||||
};
|
||||
|
||||
/* High bits */
|
||||
print_gpe_status(reset_gpe_status(GPE0_STS_2, GPE0_EN_2),
|
||||
gpe0_sts_bits_high);
|
||||
|
||||
/* Standard GPE and GPIO 0-31 */
|
||||
return print_gpe_status(reset_gpe_status(GPE0_STS, GPE0_EN),
|
||||
gpe0_sts_bits_low);
|
||||
}
|
||||
|
||||
/* Print, clear, and return LynxPoint-LP GPE0 status */
|
||||
static u32 clear_lpt_lp_gpe_status(void)
|
||||
{
|
||||
const char *gpe0_sts_4_bits[] = {
|
||||
[1] = "HOTPLUG",
|
||||
[2] = "SWGPE",
|
||||
[6] = "TCO_SCI",
|
||||
[7] = "SMB_WAK",
|
||||
[9] = "PCI_EXP",
|
||||
[10] = "BATLOW",
|
||||
[11] = "PME",
|
||||
[12] = "ME",
|
||||
[13] = "PME_B0",
|
||||
[16] = "GPIO27",
|
||||
[18] = "WADT"
|
||||
};
|
||||
|
||||
/* GPIO 0-31 */
|
||||
print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_1, LP_GPE0_EN_1), 0);
|
||||
|
||||
/* GPIO 32-63 */
|
||||
print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_2, LP_GPE0_EN_2), 32);
|
||||
|
||||
/* GPIO 64-94 */
|
||||
print_gpe_gpio(reset_gpe_status(LP_GPE0_STS_3, LP_GPE0_EN_3), 64);
|
||||
|
||||
/* Standard GPE */
|
||||
return print_gpe_status(reset_gpe_status(LP_GPE0_STS_4, LP_GPE0_EN_4),
|
||||
gpe0_sts_4_bits);
|
||||
}
|
||||
|
||||
/* Clear all GPE status and return "standard" GPE event status */
|
||||
u32 clear_gpe_status(void)
|
||||
{
|
||||
if (pch_is_lp())
|
||||
return clear_lpt_lp_gpe_status();
|
||||
else
|
||||
return clear_lpt_gpe_status();
|
||||
}
|
||||
|
||||
/* Enable all requested GPE */
|
||||
void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
|
||||
{
|
||||
u16 pmbase = get_pmbase();
|
||||
|
||||
if (pch_is_lp()) {
|
||||
outl(set1, pmbase + LP_GPE0_EN_1);
|
||||
outl(set2, pmbase + LP_GPE0_EN_2);
|
||||
outl(set3, pmbase + LP_GPE0_EN_3);
|
||||
outl(set4, pmbase + LP_GPE0_EN_4);
|
||||
} else {
|
||||
outl(set1, pmbase + GPE0_EN);
|
||||
outl(set2, pmbase + GPE0_EN_2);
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable all GPE */
|
||||
void disable_all_gpe(void)
|
||||
{
|
||||
enable_all_gpe(0, 0, 0, 0);
|
||||
}
|
||||
|
||||
/* Enable a standard GPE */
|
||||
void enable_gpe(u32 mask)
|
||||
{
|
||||
u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN;
|
||||
u32 gpe0_en = inl(get_pmbase() + gpe0_reg);
|
||||
gpe0_en |= mask;
|
||||
outl(gpe0_en, get_pmbase() + gpe0_reg);
|
||||
}
|
||||
|
||||
/* Disable a standard GPE */
|
||||
void disable_gpe(u32 mask)
|
||||
{
|
||||
u32 gpe0_reg = pch_is_lp() ? LP_GPE0_EN_4 : GPE0_EN;
|
||||
u32 gpe0_en = inl(get_pmbase() + gpe0_reg);
|
||||
gpe0_en &= ~mask;
|
||||
outl(gpe0_en, get_pmbase() + gpe0_reg);
|
||||
}
|
||||
Loading…
Reference in New Issue