From 55d47bd1bfb38aec5253529fded126e0c9238a89 Mon Sep 17 00:00:00 2001
From: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Date: Fri, 23 Sep 2022 09:59:46 +0800
Subject: [PATCH] mb/google/dedede/var/storo: Disable PCIE RP8 and CLKSRC4

This change disables unused PCIE RP8 and CLKSRC4. Without this change
storo cannot enter into s0ix properly.

BUG=b:219376808
TEST=Built and verified in storo

Change-Id: I9867825ce53de72ef73920c153002bc3be4dbd2d
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Aamir Bohra <aamirbohra@google.com>
---
 src/mainboard/google/dedede/variants/storo/overridetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 654987f40f..8aba2c8be1 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -7,6 +7,10 @@ fw_config
 end
 
 chip soc/intel/jasperlake
+	# Disable PCIe Root Port 8 (index 7)
+	register "PcieRpEnable[7]" = "0"
+	# Disable PCIe Clock Source 4 (index 3)
+	register "PcieClkSrcUsage[3]" = "0xff"
 
 	# USB Port Configuration
 	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera