src: Remove unneeded include <cbfs.h>

Change-Id: Iab0bd1c5482331a0c048a05ab806bf5c4dbda780
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29303
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/romstage.c

@@ -15,7 +15,6 @@
 
 #include <stdint.h>
 #include <string.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <arch/cpu.h>
 #include <cf9_reset.h>

src/drivers/intel/fsp1_1/ramstage.c

@@ -17,7 +17,6 @@
 #include <bootmode.h>
 #include <arch/acpi.h>
 #include <cbmem.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <fsp/memmap.h>
 #include <fsp/ramstage.h>

src/drivers/intel/fsp1_1/vbt.c

@@ -15,7 +15,6 @@
  */
 
 #include <bootmode.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <drivers/intel/gma/opregion.h>
 #include <fsp/ramstage.h>

src/drivers/intel/fsp2_0/graphics.c

@@ -10,7 +10,6 @@
  * (at your option) any later version.
  */
 
-#include <cbfs.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <soc/intel/common/vbt.h>

src/drivers/intel/fsp2_0/util.c

@@ -12,7 +12,6 @@
  */
 
 #include <arch/io.h>
-#include <cbfs.h>
 #include <cf9_reset.h>
 #include <console/console.h>
 #include <fsp/util.h>

src/drivers/spi/spi_flash.c

@@ -10,7 +10,6 @@
 #include <arch/early_variables.h>
 #include <assert.h>
 #include <boot_device.h>
-#include <cbfs.h>
 #include <cpu/x86/smm.h>
 #include <delay.h>
 #include <rules.h>

src/mainboard/asus/f2a85-m/BiosCallOuts.c

@@ -17,7 +17,6 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-#include <cbfs.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
 #include <stdlib.h>
 

src/mainboard/cubietech/cubieboard/romstage.c

@@ -24,7 +24,6 @@
  */
 
 #include <arch/stages.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <cpu/allwinner/a10/clock.h>
 #include <cpu/allwinner/a10/gpio.h>

src/mainboard/google/beltino/romstage.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <cbfs.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>

src/mainboard/google/butterfly/romstage.c

@@ -31,7 +31,6 @@
 #if IS_ENABLED(CONFIG_CHROMEOS)
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
-#include <cbfs.h>
 
 void pch_enable_lpc(void)
 {

src/mainboard/google/daisy/romstage.c

@@ -17,7 +17,6 @@
 #include <arch/exception.h>
 #include <arch/stages.h>
 #include <armv7.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <program_loading.h>

src/mainboard/google/jecht/romstage.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <cbfs.h>
 #include <console/console.h>
 #include <string.h>
 #include <ec/google/chromeec/ec.h>

src/mainboard/google/nyan/romstage.c

@@ -16,7 +16,6 @@
 #include <arch/cache.h>
 #include <arch/exception.h>
 #include <arch/io.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <reset.h>

src/mainboard/google/nyan_big/romstage.c

@@ -16,7 +16,6 @@
 #include <arch/cache.h>
 #include <arch/exception.h>
 #include <arch/io.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <reset.h>

src/mainboard/google/nyan_blaze/romstage.c

@@ -16,7 +16,6 @@
 #include <arch/cache.h>
 #include <arch/exception.h>
 #include <arch/io.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <reset.h>

src/mainboard/google/parrot/romstage.c

@@ -28,7 +28,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 #include <halt.h>
-#include <cbfs.h>
 #include "ec/compal/ene932/ec.h"
 
 void pch_enable_lpc(void)

src/mainboard/google/peach_pit/romstage.c

@@ -18,7 +18,6 @@
 #include <arch/stages.h>
 #include <armv7.h>
 #include <boot_device.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <commonlib/region.h>
 #include <console/console.h>

src/mainboard/google/stout/romstage.c

@@ -30,7 +30,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include <halt.h>
 #include <bootmode.h>
-#include <cbfs.h>
 #include <ec/quanta/it8518/ec.h>
 #include "ec.h"
 #include "onboard.h"

src/mainboard/google/veyron/romstage.c

@@ -18,7 +18,6 @@
 #include <arch/stages.h>
 #include <armv7.h>
 #include <assert.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>

src/mainboard/google/veyron_mickey/romstage.c

@@ -18,7 +18,6 @@
 #include <arch/stages.h>
 #include <armv7.h>
 #include <assert.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>

src/mainboard/google/veyron_rialto/romstage.c

@@ -19,7 +19,6 @@
 #include <arch/stages.h>
 #include <armv7.h>
 #include <assert.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>

src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c

@@ -17,7 +17,6 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-#include <cbfs.h>
 #include <southbridge/amd/agesa/hudson/imc.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
 #include <stdlib.h>

src/mainboard/intel/cannonlake_rvp/spd/spd_util.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 #include <arch/byteorder.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <stdint.h>
 #include <string.h>

src/mainboard/intel/icelake_rvp/romstage_fsp_params.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/byteorder.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <soc/romstage.h>

src/mainboard/intel/icelake_rvp/spd/spd_util.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 #include <arch/byteorder.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <stdint.h>
 #include <string.h>

src/mainboard/intel/kblrvp/spd/spd_util.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 #include <arch/byteorder.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <stdint.h>
 #include <string.h>

src/mainboard/intel/kunimitsu/romstage_fsp20.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/byteorder.h>
-#include <cbfs.h>
 #include <fsp/api.h>
 #include <gpio.h>
 #include "gpio.h"

src/mainboard/intel/kunimitsu/spd/spd.c

@@ -15,7 +15,6 @@
  */
 
 #include <arch/byteorder.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <soc/pei_data.h>
 #include <soc/romstage.h>

src/mainboard/intel/saddlebrook/romstage.c

@@ -15,7 +15,6 @@
  * GNU General Public License for more details.
  */
 
-#include <cbfs.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <string.h>

src/mainboard/intel/strago/romstage.c

@@ -14,7 +14,6 @@
  * GNU General Public License for more details.
  */
 
-#include <cbfs.h>
 #include <soc/gpio.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>

src/mainboard/lenovo/g505s/BiosCallOuts.c

@@ -17,7 +17,6 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-#include <cbfs.h>
 #include <southbridge/amd/agesa/hudson/imc.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
 #include <stdlib.h>

src/mainboard/msi/ms7721/BiosCallOuts.c

@@ -18,7 +18,6 @@
 #include <northbridge/amd/agesa/BiosCallOuts.h>
 #include <northbridge/amd/agesa/state_machine.h>
 
-#include <cbfs.h>
 #include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h>
 #include <stdlib.h>
 

src/mainboard/siemens/mc_tcu3/lcd_panel.c

@@ -12,7 +12,7 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-#include <cbfs.h>
+
 #include <console/console.h>
 #include <string.h>
 #include "soc/gpio.h"

src/mainboard/ti/beaglebone/romstage.c

@@ -16,7 +16,6 @@
 #include <types.h>
 
 #include <armv7.h>
-#include <cbfs.h>
 
 #include <program_loading.h>
 #include <console/console.h>

src/northbridge/intel/nehalem/raminit.c

@@ -21,7 +21,6 @@
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
-#include <cbfs.h>
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>

src/security/vboot/common.c

@@ -14,7 +14,6 @@
  */
 
 #include <assert.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <reset.h>
 #include <string.h>

src/security/vboot/vboot_handoff.c

@@ -26,7 +26,6 @@
 #include <assert.h>
 #include <bootmode.h>
 #include <string.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <console/vtxprintf.h>

src/soc/broadcom/cygnus/romstage.c

@@ -17,7 +17,6 @@
 #include <arch/exception.h>
 #include <arch/stages.h>
 #include <armv7.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <delay.h>

src/soc/intel/apollolake/romstage.c

@@ -22,7 +22,6 @@
 #include <arch/symbols.h>
 #include <assert.h>
 #include <bootmode.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <cf9_reset.h>
 #include <console/console.h>

src/soc/intel/baytrail/romstage/romstage.c

@@ -18,7 +18,6 @@
 #include <arch/io.h>
 #include <arch/early_variables.h>
 #include <console/console.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)

src/soc/intel/braswell/acpi.c

@@ -20,7 +20,6 @@
 #include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/smp/mpspec.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/turbo.h>

src/soc/intel/broadwell/romstage/romstage.c

@@ -20,7 +20,6 @@
 #include <arch/early_variables.h>
 #include <bootmode.h>
 #include <console/console.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
 #include <elog.h>

src/soc/intel/common/vbt.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <cbfs.h>
 #include <arch/acpi.h>
 #include <bootmode.h>
 #include <bootstate.h>

src/soc/intel/denverton_ns/memmap.c

@@ -15,7 +15,6 @@
  */
 
 #include <arch/io.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <assert.h>
 #include <device/device.h>

src/soc/mediatek/mt8173/include/soc/flash_controller.h

@@ -16,7 +16,6 @@
 #ifndef __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__
 #define __SOC_MEDIATEK_MT8173_FLASH_CONTROLLER_H__
 
-#include <cbfs.h>
 #include <spi-generic.h>
 #include <stdint.h>
 #include <soc/addressmap.h>

src/soc/nvidia/tegra124/bootblock.c

@@ -17,7 +17,6 @@
 #include <arch/exception.h>
 #include <arch/stages.h>
 #include <bootblock_common.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <program_loading.h>
 #include <soc/clock.h>

src/soc/nvidia/tegra124/spi.c

@@ -19,7 +19,6 @@
 #include <assert.h>
 #include <boot_device.h>
 #include <console/console.h>
-#include <cbfs.h>
 #include <delay.h>
 #include <inttypes.h>
 #include <soc/addressmap.h>

src/soc/nvidia/tegra210/ccplex.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/io.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <soc/addressmap.h>
 #include <soc/clock.h>

src/soc/nvidia/tegra210/romstage.c

@@ -15,7 +15,6 @@
 
 #include <arch/exception.h>
 #include <arch/stages.h>
-#include <cbfs.h>
 #include <cbmem.h>
 #include <console/cbmem_console.h>
 #include <console/console.h>

src/soc/nvidia/tegra210/spi.c

@@ -18,7 +18,6 @@
 #include <arch/io.h>
 #include <assert.h>
 #include <boot_device.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <delay.h>
 #include <inttypes.h>

src/soc/rockchip/common/i2c.c

@@ -15,7 +15,6 @@
 
 #include <arch/io.h>
 #include <assert.h>
-#include <cbfs.h>
 #include <console/console.h>
 #include <delay.h>
 #include <device/i2c_simple.h>

src/southbridge/intel/bd82x6x/early_pch.c

@@ -17,7 +17,6 @@
 #include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
-#include <cbfs.h>
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>