set up timing
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -48,11 +48,11 @@ static inline unsigned int fls(unsigned int x)
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d0_MB=1 (module banks)
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d0_cb=4 (component banks)
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do_psz=4KB (page size)
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Trc=10 (clocks)
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Tras=7
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Trcd=3
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Trp=3
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Trrd=2
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Trc=10 (clocks) (ref2act)
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Tras=7 (act2pre)
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Trcd=3 (act2cmd)
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Trp=3 (pre2act)
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Trrd=2 (act2act)
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Tref=17.8ms
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*/
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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@ -78,17 +78,15 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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HERE
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/* get the module bank density, SPD byte 31 */
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val = spd_read_byte(0xA0, 31);
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val = fls(val);
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val <<= module_banks;
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/* this is multiples of 8 MB */
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val = 128 / 8;
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msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
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/* page size = 2^col address */
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val = spd_read_byte(0xA0, 4);
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val -= 7;
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val = 2; /* 4096 bytes */
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msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
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@ -99,9 +97,23 @@ HERE
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msr.lo = 0x00003000;
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wrmsr(MC_CF07_DATA, msr);
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/* timing and mode ... */
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msr = rdmsr(0x20000019);
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msr.hi = 0x18000108;
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msr.lo = 0x696332a3;
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/* per standard bios settings */
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msr.lo =
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(6<<28) | // cas_lat
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(10<<24)| // ref2act
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(7<<20)| // act2pre
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(3<<16)| // pre2act
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(3<<12)| // act2cmd
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(2<<8)| // act2act
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(2<<6)| // dplwr
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(2<<4)| // dplrd
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(3); // dal
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wrmsr(0x20000019, msr);
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}
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