mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config

This patch enables lockdown configuration for saddlebrook platform

BUG=None
TEST=Boot to Linux on saddlebrook and verified MRC is restored on warm, cold,
	resume boot path's.

Change-Id: Ia324c118b0c8e72b66a757dee5be43ba79abbeab
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/intel/saddlebrook/devicetree.cb

@@ -61,6 +61,11 @@ chip soc/intel/skylake
 
 	register "serirq_mode" = "SERIRQ_CONTINUOUS"
 
+	# Lock Down
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+	}"
+
 	# VR Settings Configuration for 4 Domains
 	#+----------------+-----------+-----------+-------------+----------+
 	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |