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soc/intel/alderlake: Implement report_cache_info() function 

Make use of deterministic cache helper functions from Alder Lake
SoC code to print useful information during boot as below:

Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384
Cache size = 12 MiB

Change-Id: I30a56266015d69abccb885b3f230689488ee0360
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik 2021-07-23 21:04:41 +05:30
parent e2b5fee3b0
commit 55f5410fcd
1 changed files with 18 additions and 0 deletions
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18
src/soc/intel/alderlake/bootblock/report_platform.c
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@ -8,6 +8,7 @@
#include <arch/cpu.h>
#include <device/pci_ops.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <cpu/intel/cpu_ids.h>
#include <cpu/intel/microcode.h>
@ -120,6 +121,21 @@ static inline uint16_t get_dev_id(pci_devfn_t dev)
return pci_read_config16(dev, PCI_DEVICE_ID);
}
static void report_cache_info(void)
{
int cache_level = CACHE_L3;
struct cpu_cache_info info;
if (!fill_cpu_cache_info(cache_level, &info))
return;
printk(BIOS_INFO, "Cache: Level %d: ", cache_level);
printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n",
info.num_ways, info.physical_partitions, info.line_size, info.num_sets);
printk(BIOS_INFO, "Cache size = %ld MiB\n", get_cache_size(&info)/MiB);
}
static void report_cpu_info(void)
{
u32 i, cpu_id, cpu_feature_flag;
@ -150,6 +166,8 @@ static void report_cpu_info(void)
printk(BIOS_DEBUG,
"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
report_cache_info();
}
static void report_mch_info(void)