soc/intel/alderlake: Implement report_cache_info() function
Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache size = 12 MiB Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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@ -8,6 +8,7 @@
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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#include <device/pci_ops.h>
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#include <device/pci_ops.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cpu/intel/cpu_ids.h>
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#include <cpu/intel/cpu_ids.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/microcode.h>
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@ -120,6 +121,21 @@ static inline uint16_t get_dev_id(pci_devfn_t dev)
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return pci_read_config16(dev, PCI_DEVICE_ID);
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return pci_read_config16(dev, PCI_DEVICE_ID);
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}
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}
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static void report_cache_info(void)
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{
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int cache_level = CACHE_L3;
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struct cpu_cache_info info;
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if (!fill_cpu_cache_info(cache_level, &info))
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return;
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printk(BIOS_INFO, "Cache: Level %d: ", cache_level);
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printk(BIOS_INFO, "Associativity = %zd Partitions = %zd Line Size = %zd Sets = %zd\n",
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info.num_ways, info.physical_partitions, info.line_size, info.num_sets);
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printk(BIOS_INFO, "Cache size = %ld MiB\n", get_cache_size(&info)/MiB);
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}
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static void report_cpu_info(void)
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static void report_cpu_info(void)
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{
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{
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u32 i, cpu_id, cpu_feature_flag;
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u32 i, cpu_id, cpu_feature_flag;
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@ -150,6 +166,8 @@ static void report_cpu_info(void)
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printk(BIOS_DEBUG,
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printk(BIOS_DEBUG,
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"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
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"CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n",
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mode[aes], mode[txt], mode[vt]);
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mode[aes], mode[txt], mode[vt]);
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report_cache_info();
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}
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}
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static void report_mch_info(void)
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static void report_mch_info(void)
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