VX900: Use MIN/MAX from stdlib.h instead of redefining them

Change-Id: I2dd693b300085493baa65bb652df8d6cce80b63b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/3431
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/northbridge/via/vx900/chrome9hd.c

@@ -23,6 +23,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <pc80/vga_io.h>
+#include <stdlib.h>
 
 #include "vx900.h"
 
@@ -79,7 +80,7 @@ u32 chrome9hd_fb_size(void)
 	size_mb = 512;
 
 	/* The minimum framebuffer size is 8MB. */
-	size_mb = max(size_mb, CHROME_9_HD_MIN_FB_SIZE);
+	size_mb = MAX(size_mb, CHROME_9_HD_MIN_FB_SIZE);
 
 	const device_t mcu = dev_find_device(PCI_VENDOR_ID_VIA,
 					     PCI_DEVICE_ID_VIA_VX900_MEMCTRL,
@@ -203,6 +204,7 @@ u8 vx900_int15_get_5f18_bl(void)
 
 	return ret;
 }
+
 /** @} */
 
 static void chrome9hd_set_sid_vid(u16 vendor, u16 device)

src/northbridge/via/vx900/northbridge.c

@@ -191,7 +191,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
 	}
 
 	/* The "remap to where?" register */
-	reg32 = ((max(tor, RAM_4GB) >> 26) & 0x3ff) << 2;
+	reg32 = ((MAX(tor, RAM_4GB) >> 26) & 0x3ff) << 2;
 	/* The "remap until where?" register */
 	reg32 |= ((newtor >> 26) & 0x3ff) << 14;
 	/* Now enable the goodies */
@@ -238,7 +238,7 @@ static void vx900_set_resources(device_t dev)
 	vx900_tolm = (pci_read_config16(mcu, 0x84) & 0xfff0) >> 4;
 	full_tolmk = vx900_tolm << (20 - 10);
 	/* Remap above 4G if needed */
-	full_tolmk = min(full_tolmk, pci_tolm >> 10);
+	full_tolmk = MIN(full_tolmk, pci_tolm >> 10);
 	printk(BIOS_SPEW, "Found top of low memory at  %dMB\n",
 	       full_tolmk >> 10);
 
@@ -247,7 +247,7 @@ static void vx900_set_resources(device_t dev)
 	printk(BIOS_SPEW, "Integrated graphics buffer: %dMB\n", fbufk >> 10);
 
 	/* Can't use the framebuffer as system RAM, sorry */
-	tolmk = min(full_tolmk, tomk);
+	tolmk = MIN(full_tolmk, tomk);
 	tolmk -= fbufk;
 	ram_resource(dev, idx++, 0, 640);
 	printk(BIOS_SPEW, "System ram left:            %dMB\n", tolmk >> 10);

src/northbridge/via/vx900/raminit_ddr3.c

@@ -378,18 +378,18 @@ static void dram_find_common_params(const dimm_info * dimms,
 		ctrl->cas_supported &= dimm->cas_supported;
 
 		/* Find the smallest common latencies supported by all DIMMs */
-		ctrl->tCK = max(ctrl->tCK, dimm->tCK);
+		ctrl->tCK = MAX(ctrl->tCK, dimm->tCK);
-		ctrl->tAA = max(ctrl->tAA, dimm->tAA);
+		ctrl->tAA = MAX(ctrl->tAA, dimm->tAA);
-		ctrl->tWR = max(ctrl->tWR, dimm->tWR);
+		ctrl->tWR = MAX(ctrl->tWR, dimm->tWR);
-		ctrl->tRCD = max(ctrl->tRCD, dimm->tRCD);
+		ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD);
-		ctrl->tRRD = max(ctrl->tRRD, dimm->tRRD);
+		ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD);
-		ctrl->tRP = max(ctrl->tRP, dimm->tRP);
+		ctrl->tRP = MAX(ctrl->tRP, dimm->tRP);
-		ctrl->tRAS = max(ctrl->tRAS, dimm->tRAS);
+		ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS);
-		ctrl->tRC = max(ctrl->tRC, dimm->tRC);
+		ctrl->tRC = MAX(ctrl->tRC, dimm->tRC);
-		ctrl->tRFC = max(ctrl->tRFC, dimm->tRFC);
+		ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC);
-		ctrl->tWTR = max(ctrl->tWTR, dimm->tWTR);
+		ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR);
-		ctrl->tRTP = max(ctrl->tRTP, dimm->tRTP);
+		ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP);
-		ctrl->tFAW = max(ctrl->tFAW, dimm->tFAW);
+		ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW);
 
 	}
 
@@ -1048,10 +1048,10 @@ static void vx900_dram_find_avg_delays(vx900_delay_calib * delays)
 	delay_range *tx_dqs_b = &(delays->tx_dqs[1]);
 
 	for (i = 0; i < 8; i++) {
-		dq_low = max(tx_dq_a->low[i], tx_dq_b->low[i]);
+		dq_low = MAX(tx_dq_a->low[i], tx_dq_b->low[i]);
-		dq_high = min(tx_dq_a->high[i], tx_dq_b->high[i]);
+		dq_high = MIN(tx_dq_a->high[i], tx_dq_b->high[i]);
-		dqs_low = max(tx_dqs_a->low[i], tx_dqs_b->low[i]);
+		dqs_low = MAX(tx_dqs_a->low[i], tx_dqs_b->low[i]);
-		dqs_high = min(tx_dqs_a->high[i], tx_dqs_b->high[i]);
+		dqs_high = MIN(tx_dqs_a->high[i], tx_dqs_b->high[i]);
 
 		/* Find the average */
 		dq_final = ((dq_low + dq_high) / 2);
@@ -1540,7 +1540,7 @@ static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks)
 	/* Limit the Top of Low memory at 3.5G
 	 * Not to worry, we'll set tolm in ramstage, once we have initialized
 	 * all devices and know pci_tolm. */
-	tolm_mb = min(ramsize_mb, TOLM_3_5G >> 20);
+	tolm_mb = MIN(ramsize_mb, TOLM_3_5G >> 20);
 	u16 reg_tolm = (tolm_mb << 4) & 0xfff0;
 	pci_mod_config16(MCU, 0x84, 0xfff0, reg_tolm);
 
@@ -1587,7 +1587,7 @@ static void vx900_dram_map_row_col_bank(dimm_info * dimms)
 		reg8 |= (rcb_val << ((i * 3) + 2));
 
 		/* */
-		max_row_bits = max(max_row_bits, dimms->dimm[i].row_bits);
+		max_row_bits = MAX(max_row_bits, dimms->dimm[i].row_bits);
 	}
 
 	printram("RCBA map (rx50) <- %.2x\n", reg8);

src/northbridge/via/vx900/vx900.h

@@ -33,9 +33,6 @@
 #define VX900_MAX_DIMM_SLOTS 2
 #define VX900_MAX_MEM_RANKS 4
 
-#define min(a,b) (a<b?a:b)
-#define max(a,b) (a>b?a:b)
-
 #include <arch/io.h>
 #include <device/pci.h>