aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG
Both SMM_ASEG and SMM_TSEG choices work. There is periodic TCO timeout occurring. At least with DEBUG_SMI kernel reports low memory corruption. Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
parent
0c745347d0
commit
560c3f5ccf
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@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_F2X
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select SUPPORT_CPU_UCODE_IN_CBFS
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select CPU_INTEL_COMMON
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select SSE2
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select NO_SMM
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@ -1,5 +1,6 @@
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subdirs-y += ../common
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ramstage-y += model_f2x_init.c
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ramstage-y += mp_init.c
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cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*)
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@ -2,9 +2,6 @@
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#include <device/device.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/common/common.h>
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#include <cpu/x86/cache.h>
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@ -32,36 +29,3 @@ static const struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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/* Parallel MP initialization support. */
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static void pre_mp_init(void)
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{
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const void *patch = intel_microcode_find();
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intel_microcode_load_unlocked(patch);
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/* Setup MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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static int get_cpu_count(void)
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{
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return CONFIG_MAX_CPUS;
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}
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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*microcode = intel_microcode_find();
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*parallel = !intel_ht_supported();
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_microcode_info = get_microcode_info,
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};
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void mp_init_cpus(struct bus *cpu_bus)
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{
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mp_init_with_smm(cpu_bus, &mp_ops);
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}
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@ -0,0 +1,105 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <cpu/intel/microcode.h>
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/intel/common/common.h>
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#include <cpu/x86/legacy_save_state.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/mp.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <types.h>
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/* Parallel MP initialization support. */
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static void pre_mp_init(void)
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{
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const void *patch = intel_microcode_find();
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intel_microcode_load_unlocked(patch);
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/* Setup MTRRs based on physical address size. */
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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static int get_cpu_count(void)
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{
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return CONFIG_MAX_CPUS;
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}
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static void get_microcode_info(const void **microcode, int *parallel)
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{
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*microcode = intel_microcode_find();
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*parallel = !intel_ht_supported();
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}
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static void pre_mp_smm_init(void)
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{
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/* Clear the SMM state in the southbridge. */
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smm_southbridge_clear_state();
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/*
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* Run the relocation handler for on the BSP to check and set up
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* parallel SMM relocation.
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*/
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smm_initiate_relocation();
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}
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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smm_open();
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
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*smm_save_state_size = sizeof(legacy_smm_state_save_area_t);
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printk(BIOS_DEBUG, "Save state size: 0x%zx bytes\n", *smm_save_state_size);
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}
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/*
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* The relocation work is actually performed in SMM context, but the code
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* resides in the ramstage module. This occurs by trampolining from the default
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* SMRAM entry point to here.
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*/
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static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase)
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{
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legacy_smm_state_save_area_t *save_state;
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u32 smbase = staggered_smbase;
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save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
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save_state->smbase = smbase;
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printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
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printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", save_state->smm_revision);
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printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase);
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}
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static void post_mp_init(void)
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{
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smm_close();
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/* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */
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global_smi_enable();
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/* Lock down the SMRAM space. */
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smm_lock();
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.get_microcode_info = get_microcode_info,
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.pre_mp_smm_init = pre_mp_smm_init,
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/* .per_cpu_smm_trigger = smm_initiate_relocation, using default */
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.relocation_handler = relocation_handler,
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.post_mp_init = post_mp_init,
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};
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void mp_init_cpus(struct bus *cpu_bus)
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{
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/* TODO: Handle mp_init_with_smm failure? */
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mp_init_with_smm(cpu_bus, &mp_ops);
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}
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@ -10,5 +10,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
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select NO_ECAM_MMCONF_SUPPORT
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select HAVE_DEBUG_RAM_SETUP
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select NO_CBFS_MCACHE
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select SMM_TSEG
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endif
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@ -7,6 +7,11 @@
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#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H
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#define NORTHBRIDGE_INTEL_E7505_E7505_H
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#include <types.h>
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size_t northbridge_get_tseg_size(void);
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uintptr_t northbridge_get_tseg_base(void);
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/************ D0:F0 ************/
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// Register offsets
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#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */
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@ -28,8 +33,6 @@
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#define DRC 0x7C /* DRAM Controller Mode register, 32 bit */
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#define DRDCTL 0x80 /* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
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#define CKDIS 0x8C /* Clock disable register, 8 bit */
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#define SMRAMC 0x9D
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#define ESMRAMC 0x9E
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#define APSIZE 0xB4
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#define TOLM 0xC4 /* Top of Low Memory register, 16 bit */
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#define REMAPBASE 0xC6 /* Remap Base Address register, 16 bit */
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@ -38,6 +41,22 @@
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#define DVNP 0xE0 /* Device Not Present, 16 bit */
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#define MCHTST 0xF4 /* MCH Test Register, 32 bit? (if similar to 855PM) */
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#define SMRAMC 0x9D
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define G_SMRAME (1 << 3)
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#define D_LCK (1 << 4)
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#define D_CLS (1 << 5)
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#define D_OPEN (1 << 6)
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#define ESMRAMC 0x9E
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#define T_EN (1 << 0)
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#define TSEG_SZ_128K (0 << 1)
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#define TSEG_SZ_256K (1 << 1)
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#define TSEG_SZ_512K (2 << 1)
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#define TSEG_SZ_1M (3 << 1)
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#define TSEG_SZ_MASK TSEG_SZ_1M
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#define H_SMRAME (1 << 7)
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// CAS# Latency bits in the DRAM Timing (DRT) register
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#define DRT_CAS_2_5 (0<<4)
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#define DRT_CAS_2_0 (1<<4)
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@ -5,37 +5,93 @@
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#include <arch/romstage.h>
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#include <cbmem.h>
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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#include <program_loading.h>
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#include <stdint.h>
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#include "e7505.h"
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uintptr_t cbmem_top_chipset(void)
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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static uintptr_t top_of_low_ram(void)
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{
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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uintptr_t tolm;
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/* This is at 128 MiB boundary. */
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tolm = pci_read_config16(mch, TOLM) >> 11;
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tolm = pci_read_config16(HOST_BRIDGE, TOLM) >> 11;
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tolm <<= 27;
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return tolm;
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}
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void northbridge_write_smram(u8 smram);
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void northbridge_write_smram(u8 smram)
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size_t northbridge_get_tseg_size(void)
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{
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const pci_devfn_t mch = PCI_DEV(0, 0, 0);
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pci_write_config8(mch, SMRAMC, smram);
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const uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
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if (!(esmramc & T_EN))
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return 0;
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switch ((esmramc & TSEG_SZ_MASK) >> 1) {
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case 0:
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return 128 * KiB;
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case 1:
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return 256 * KiB;
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case 2:
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return 512 * KiB;
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case 3:
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default:
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return 1 * MiB;
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}
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}
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uintptr_t northbridge_get_tseg_base(void)
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{
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uintptr_t tolm = top_of_low_ram();
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/* subtract TSEG size */
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tolm -= northbridge_get_tseg_size();
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return tolm;
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}
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void smm_region(uintptr_t *start, size_t *size)
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{
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*start = northbridge_get_tseg_base();
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*size = northbridge_get_tseg_size();
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}
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uintptr_t cbmem_top_chipset(void)
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{
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return northbridge_get_tseg_base();
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}
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void smm_open(void)
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{
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/* Set D_OPEN */
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pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG);
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}
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void smm_close(void)
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{
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/* Clear D_OPEN */
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pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG);
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}
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void smm_lock(void)
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{
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/*
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* LOCK the SMM memory window and enable normal SMM.
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* After running this function, only a full reset can
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
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}
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void fill_postcar_frame(struct postcar_frame *pcf)
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{
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uintptr_t top_of_ram;
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/*
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* Choose to NOT set ROM as WP cacheable here.
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* Timestamps indicate the CPU this northbridge code is
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@ -45,11 +101,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
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pcf->skip_common_mtrr = 1;
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/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
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postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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/* Cache CBMEM region as WB. */
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top_of_ram = (uintptr_t)cbmem_top();
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postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
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MTRR_TYPE_WRBACK);
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/* Cache RAM as WB from 0 -> TOLM. */
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postcar_frame_add_mtrr(pcf, top_of_low_ram(), CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
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}
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@ -42,6 +42,9 @@ static void mch_domain_read_resources(struct device *dev)
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ram_resource_kb(dev, idx++, 0, tolmk);
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mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
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uintptr_t tseg_memory_base = northbridge_get_tseg_base();
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size_t tseg_memory_size = northbridge_get_tseg_size();
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mmio_resource_kb(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
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ASSERT(tom == remapbase);
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upper_ram_end(dev, idx++, remaplimit);
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@ -1687,6 +1687,8 @@ static int e7505_mch_is_ready(void)
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return !!(dword & DRC_DONE);
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}
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#define HOST_BRIDGE PCI_DEV(0, 0, 0)
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void sdram_initialize(void)
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{
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static const struct mem_controller memctrl[] = {
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@ -1714,5 +1716,9 @@ void sdram_initialize(void)
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timestamp_add_now(TS_INITRAM_END);
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}
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if (CONFIG(SMM_TSEG))
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pci_write_config8(HOST_BRIDGE, ESMRAMC, TSEG_SZ_1M | T_EN);
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printk(BIOS_DEBUG, "SDRAM is up.\n");
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}
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@ -3,7 +3,9 @@
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config SOUTHBRIDGE_INTEL_I82801DX
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bool
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select ACPI_INTEL_HARDWARE_SLEEP_VALUES
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select HAVE_SMI_HANDLER
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select SOUTHBRIDGE_INTEL_COMMON_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_SMM
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select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
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select SOUTHBRIDGE_INTEL_COMMON_RTC
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select SOUTHBRIDGE_INTEL_COMMON_RESET
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@ -15,4 +15,6 @@ ramstage-y += lpc.c
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ramstage-y += usb.c
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ramstage-y += usb2.c
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smm-y += smihandler.c
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endif
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@ -1,20 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/pci_ops.h>
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#include <acpi/acpi.h>
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#include <version.h>
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/* FIXME: This needs to go into a separate .h file
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* to be included by the ich7 smi handler, ich7 smi init
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* code and the mainboard fadt.
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*/
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#define APM_CNT 0x0 /* ACPI mode only */
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#define CST_CONTROL 0x85
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#define PST_CONTROL 0x0
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#define ACPI_DISABLE 0xAA
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#define ACPI_ENABLE 0x55
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#define S4_BIOS 0x77
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#define GNVS_UPDATE 0xea
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#include <cpu/x86/smm.h>
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#include <device/pci_ops.h>
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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@ -24,9 +12,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
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if (permanent_smi_handler()) {
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fadt->smi_cmd = APM_CNT;
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fadt->acpi_enable = ACPI_ENABLE;
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fadt->acpi_disable = ACPI_DISABLE;
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fadt->pstate_cnt = PST_CONTROL;
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fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
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fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
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}
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fadt->pm1a_evt_blk = pmbase;
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@ -140,8 +140,8 @@ void i82801dx_lpc_setup(void);
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#define DEVACT_STS 0x44
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#define SS_CNT 0x50
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#define TCOBASE 0x60 /* TCO Base Address Register */
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#define TCO1_CNT 0x08 /* TCO1 Control Register */
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/* TCO1 Control Register */
|
||||
#define TCO1_CNT 0x68
|
||||
|
||||
#define GEN_PMCON_1 0xa0
|
||||
#define GEN_PMCON_2 0xa2
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#include <arch/io.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
|
@ -162,6 +163,15 @@ static void i82801dx_rtc_init(struct device *dev)
|
|||
pci_write_config8(dev, RTC_CONF, 0x04);
|
||||
}
|
||||
|
||||
static void i82801dx_set_acpi_mode(struct device *dev)
|
||||
{
|
||||
if (!acpi_is_wakeup_s3()) {
|
||||
apm_control(APM_CNT_ACPI_DISABLE);
|
||||
} else {
|
||||
apm_control(APM_CNT_ACPI_ENABLE);
|
||||
}
|
||||
}
|
||||
|
||||
static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
|
||||
{
|
||||
u16 reg16;
|
||||
|
|
@ -240,6 +250,8 @@ static void lpc_init(struct device *dev)
|
|||
enable_hpet(dev);
|
||||
|
||||
setup_i8259();
|
||||
|
||||
i82801dx_set_acpi_mode(dev);
|
||||
}
|
||||
|
||||
static void i82801dx_lpc_read_resources(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <southbridge/intel/common/pmutil.h>
|
||||
#include "i82801dx.h"
|
||||
|
||||
void southbridge_smi_monitor(void)
|
||||
{
|
||||
}
|
||||
|
||||
void southbridge_finalize_all(void)
|
||||
{
|
||||
}
|
||||
Loading…
Reference in New Issue