aopen/dxplplusu: Support SMM_ASEG and SMM_TSEG

Both SMM_ASEG and SMM_TSEG choices work.

There is periodic TCO timeout occurring.
At least with DEBUG_SMI kernel reports low memory corruption.

Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/cpu/intel/model_f2x/Kconfig

@@ -4,4 +4,3 @@ config CPU_INTEL_MODEL_F2X
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
 	select SSE2
-	select NO_SMM

src/cpu/intel/model_f2x/Makefile.inc

@@ -1,5 +1,6 @@
 subdirs-y += ../common
 
 ramstage-y += model_f2x_init.c
+ramstage-y += mp_init.c
 
 cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-02-*)

src/cpu/intel/model_f2x/model_f2x_init.c

@@ -2,9 +2,6 @@
 
 #include <device/device.h>
 #include <cpu/cpu.h>
-#include <cpu/x86/mp.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/intel/microcode.h>
 #include <cpu/intel/common/common.h>
 #include <cpu/x86/cache.h>
 
@@ -32,36 +29,3 @@ static const struct cpu_driver driver __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
 };
-
-/* Parallel MP initialization support. */
-static void pre_mp_init(void)
-{
-	const void *patch = intel_microcode_find();
-	intel_microcode_load_unlocked(patch);
-
-	/* Setup MTRRs based on physical address size. */
-	x86_setup_mtrrs_with_detect();
-	x86_mtrr_check();
-}
-
-static int get_cpu_count(void)
-{
-	return CONFIG_MAX_CPUS;
-}
-
-static void get_microcode_info(const void **microcode, int *parallel)
-{
-	*microcode = intel_microcode_find();
-	*parallel = !intel_ht_supported();
-}
-
-static const struct mp_ops mp_ops = {
-	.pre_mp_init = pre_mp_init,
-	.get_cpu_count = get_cpu_count,
-	.get_microcode_info = get_microcode_info,
-};
-
-void mp_init_cpus(struct bus *cpu_bus)
-{
-	mp_init_with_smm(cpu_bus, &mp_ops);
-}

src/cpu/intel/model_f2x/mp_init.c

@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
+#include <cpu/x86/legacy_save_state.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/mp.h>
+#include <device/device.h>
+#include <device/pci_ops.h>
+#include <types.h>
+
+/* Parallel MP initialization support. */
+static void pre_mp_init(void)
+{
+	const void *patch = intel_microcode_find();
+	intel_microcode_load_unlocked(patch);
+
+	/* Setup MTRRs based on physical address size. */
+	x86_setup_mtrrs_with_detect();
+	x86_mtrr_check();
+}
+
+static int get_cpu_count(void)
+{
+	return CONFIG_MAX_CPUS;
+}
+
+static void get_microcode_info(const void **microcode, int *parallel)
+{
+	*microcode = intel_microcode_find();
+	*parallel = !intel_ht_supported();
+}
+
+static void pre_mp_smm_init(void)
+{
+	/* Clear the SMM state in the southbridge. */
+	smm_southbridge_clear_state();
+
+	/*
+	 * Run the relocation handler for on the BSP to check and set up
+	 * parallel SMM relocation.
+	 */
+	smm_initiate_relocation();
+}
+
+static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
+	      size_t *smm_save_state_size)
+{
+	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
+
+	smm_open();
+
+	smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
+
+	*smm_save_state_size = sizeof(legacy_smm_state_save_area_t);
+	printk(BIOS_DEBUG, "Save state size: 0x%zx bytes\n", *smm_save_state_size);
+}
+
+/*
+ * The relocation work is actually performed in SMM context, but the code
+ * resides in the ramstage module. This occurs by trampolining from the default
+ * SMRAM entry point to here.
+ */
+static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase)
+{
+	legacy_smm_state_save_area_t *save_state;
+	u32 smbase = staggered_smbase;
+
+	save_state = (void *)(curr_smbase + SMM_DEFAULT_SIZE - sizeof(*save_state));
+	save_state->smbase = smbase;
+
+	printk(BIOS_DEBUG, "In relocation handler: cpu %d\n", cpu);
+	printk(BIOS_DEBUG, "SMM revision: 0x%08x\n", save_state->smm_revision);
+	printk(BIOS_DEBUG, "New SMBASE=0x%08x\n", smbase);
+}
+
+static void post_mp_init(void)
+{
+	smm_close();
+
+	/* Now that all APs have been relocated as well as the BSP let SMIs start flowing. */
+	global_smi_enable();
+
+	/* Lock down the SMRAM space. */
+	smm_lock();
+}
+
+static const struct mp_ops mp_ops = {
+	.pre_mp_init = pre_mp_init,
+	.get_cpu_count = get_cpu_count,
+	.get_smm_info = get_smm_info,
+	.get_microcode_info = get_microcode_info,
+	.pre_mp_smm_init = pre_mp_smm_init,
+	/* .per_cpu_smm_trigger = smm_initiate_relocation, using default */
+	.relocation_handler = relocation_handler,
+	.post_mp_init = post_mp_init,
+};
+
+void mp_init_cpus(struct bus *cpu_bus)
+{
+	/* TODO: Handle mp_init_with_smm failure? */
+	mp_init_with_smm(cpu_bus, &mp_ops);
+}

src/northbridge/intel/e7505/Kconfig

@@ -10,5 +10,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS
 	select NO_ECAM_MMCONF_SUPPORT
 	select HAVE_DEBUG_RAM_SETUP
 	select NO_CBFS_MCACHE
+	select SMM_TSEG
 
 endif

src/northbridge/intel/e7505/e7505.h

@@ -7,6 +7,11 @@
 #ifndef NORTHBRIDGE_INTEL_E7505_E7505_H
 #define NORTHBRIDGE_INTEL_E7505_E7505_H
 
+#include <types.h>
+
+size_t northbridge_get_tseg_size(void);
+uintptr_t northbridge_get_tseg_base(void);
+
 /************  D0:F0 ************/
 // Register offsets
 #define SMRBASE		0x14	/* System Memory RCOMP Base Address Register, 32 bit? */
@@ -28,8 +33,6 @@
 #define DRC		0x7C	/* DRAM Controller Mode register, 32 bit */
 #define DRDCTL		0x80	/* DRAM Read Timing Control register, 16 bit? (if similar to 855PM) */
 #define CKDIS		0x8C	/* Clock disable register, 8 bit */
-#define SMRAMC		0x9D
-#define ESMRAMC		0x9E
 #define APSIZE		0xB4
 #define TOLM		0xC4	/* Top of Low Memory register, 16 bit */
 #define REMAPBASE	0xC6	/* Remap Base Address register, 16 bit */
@@ -38,6 +41,22 @@
 #define DVNP		0xE0	/* Device Not Present, 16 bit */
 #define MCHTST		0xF4	/* MCH Test Register, 32 bit? (if similar to 855PM) */
 
+#define SMRAMC		0x9D
+#define C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+#define G_SMRAME	(1 << 3)
+#define	D_LCK		(1 << 4)
+#define D_CLS		(1 << 5)
+#define D_OPEN		(1 << 6)
+
+#define ESMRAMC		0x9E
+#define T_EN		(1 << 0)
+#define	TSEG_SZ_128K	(0 << 1)
+#define TSEG_SZ_256K	(1 << 1)
+#define TSEG_SZ_512K	(2 << 1)
+#define TSEG_SZ_1M	(3 << 1)
+#define TSEG_SZ_MASK	TSEG_SZ_1M
+#define H_SMRAME	(1 << 7)
+
 // CAS# Latency bits in the DRAM Timing (DRT) register
 #define DRT_CAS_2_5		(0<<4)
 #define DRT_CAS_2_0		(1<<4)

src/northbridge/intel/e7505/memmap.c

@@ -5,37 +5,93 @@
 
 #include <arch/romstage.h>
 #include <cbmem.h>
+#include <cpu/intel/smm_reloc.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/smm.h>
 #include <device/pci_ops.h>
 #include <program_loading.h>
 #include <stdint.h>
 
 #include "e7505.h"
 
-uintptr_t cbmem_top_chipset(void)
+#define HOST_BRIDGE PCI_DEV(0, 0, 0)
+
+static uintptr_t top_of_low_ram(void)
 {
-	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
 	uintptr_t tolm;
 
 	/* This is at 128 MiB boundary. */
-	tolm = pci_read_config16(mch, TOLM) >> 11;
+	tolm = pci_read_config16(HOST_BRIDGE, TOLM) >> 11;
 	tolm <<= 27;
-
 	return tolm;
 }
 
-void northbridge_write_smram(u8 smram);
+size_t northbridge_get_tseg_size(void)
-
-void northbridge_write_smram(u8 smram)
 {
-	const pci_devfn_t mch = PCI_DEV(0, 0, 0);
+	const uint8_t esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC);
-	pci_write_config8(mch, SMRAMC, smram);
+
+	if (!(esmramc & T_EN))
+		return 0;
+
+	switch ((esmramc & TSEG_SZ_MASK) >> 1) {
+	case 0:
+		return 128 * KiB;
+	case 1:
+		return 256 * KiB;
+	case 2:
+		return 512 * KiB;
+	case 3:
+	default:
+		return 1 * MiB;
+	}
+}
+
+uintptr_t northbridge_get_tseg_base(void)
+{
+	uintptr_t tolm = top_of_low_ram();
+
+	/* subtract TSEG size */
+	tolm -= northbridge_get_tseg_size();
+	return tolm;
+}
+
+void smm_region(uintptr_t *start, size_t *size)
+{
+	*start = northbridge_get_tseg_base();
+	*size = northbridge_get_tseg_size();
+}
+
+uintptr_t cbmem_top_chipset(void)
+{
+	return northbridge_get_tseg_base();
+}
+
+void smm_open(void)
+{
+	/* Set D_OPEN */
+	pci_write_config8(HOST_BRIDGE, SMRAMC, D_OPEN | G_SMRAME | C_BASE_SEG);
+}
+
+void smm_close(void)
+{
+	/* Clear D_OPEN */
+	pci_write_config8(HOST_BRIDGE, SMRAMC, G_SMRAME | C_BASE_SEG);
+}
+
+void smm_lock(void)
+{
+	/*
+	 * LOCK the SMM memory window and enable normal SMM.
+	 * After running this function, only a full reset can
+	 * make the SMM registers writable again.
+	 */
+	printk(BIOS_DEBUG, "Locking SMM.\n");
+
+	pci_write_config8(HOST_BRIDGE, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG);
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
-
 	/*
 	 * Choose to NOT set ROM as WP cacheable here.
 	 * Timestamps indicate the CPU this northbridge code is
@@ -45,11 +101,6 @@ void fill_postcar_frame(struct postcar_frame *pcf)
 
 	pcf->skip_common_mtrr = 1;
 
-	/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
+	/* Cache RAM as WB from 0 -> TOLM. */
-	postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
+	postcar_frame_add_mtrr(pcf, top_of_low_ram(), CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);
-
-	/* Cache CBMEM region as WB. */
-	top_of_ram = (uintptr_t)cbmem_top();
-	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB,
-		MTRR_TYPE_WRBACK);
 }

src/northbridge/intel/e7505/northbridge.c

@@ -42,6 +42,9 @@ static void mch_domain_read_resources(struct device *dev)
 	ram_resource_kb(dev, idx++, 0, tolmk);
 	mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
 
+	uintptr_t tseg_memory_base = northbridge_get_tseg_base();
+	size_t tseg_memory_size = northbridge_get_tseg_size();
+	mmio_resource_kb(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
 
 	ASSERT(tom == remapbase);
 	upper_ram_end(dev, idx++, remaplimit);

src/northbridge/intel/e7505/raminit.c

@@ -1687,6 +1687,8 @@ static int e7505_mch_is_ready(void)
 	return !!(dword & DRC_DONE);
 }
 
+#define HOST_BRIDGE PCI_DEV(0, 0, 0)
+
 void sdram_initialize(void)
 {
 	static const struct mem_controller memctrl[] = {
@@ -1714,5 +1716,9 @@ void sdram_initialize(void)
 		timestamp_add_now(TS_INITRAM_END);
 	}
 
+
+	if (CONFIG(SMM_TSEG))
+		pci_write_config8(HOST_BRIDGE, ESMRAMC, TSEG_SZ_1M | T_EN);
+
 	printk(BIOS_DEBUG, "SDRAM is up.\n");
 }

src/southbridge/intel/i82801dx/Kconfig

@@ -3,7 +3,9 @@
 config SOUTHBRIDGE_INTEL_I82801DX
 	bool
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select HAVE_SMI_HANDLER
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
+	select SOUTHBRIDGE_INTEL_COMMON_SMM
 	select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_RTC
 	select SOUTHBRIDGE_INTEL_COMMON_RESET

src/southbridge/intel/i82801dx/Makefile.inc

@@ -15,4 +15,6 @@ ramstage-y += lpc.c
 ramstage-y += usb.c
 ramstage-y += usb2.c
 
+smm-y += smihandler.c
+
 endif

src/southbridge/intel/i82801dx/fadt.c

@@ -1,20 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <device/pci_ops.h>
 #include <acpi/acpi.h>
-#include <version.h>
+#include <cpu/x86/smm.h>
-
+#include <device/pci_ops.h>
-/* FIXME: This needs to go into a separate .h file
- * to be included by the ich7 smi handler, ich7 smi init
- * code and the mainboard fadt.
- */
-#define APM_CNT		0x0   /* ACPI mode only */
-#define   CST_CONTROL	0x85
-#define   PST_CONTROL	0x0
-#define   ACPI_DISABLE	0xAA
-#define   ACPI_ENABLE	0x55
-#define   S4_BIOS	0x77
-#define   GNVS_UPDATE   0xea
 
 void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
@@ -24,9 +12,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	if (permanent_smi_handler()) {
 		fadt->smi_cmd = APM_CNT;
-		fadt->acpi_enable = ACPI_ENABLE;
+		fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
-		fadt->acpi_disable = ACPI_DISABLE;
+		fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
-		fadt->pstate_cnt = PST_CONTROL;
 	}
 
 	fadt->pm1a_evt_blk = pmbase;

src/southbridge/intel/i82801dx/i82801dx.h

@@ -140,8 +140,8 @@ void i82801dx_lpc_setup(void);
 #define DEVACT_STS	0x44
 #define SS_CNT		0x50
 
-#define TCOBASE		0x60 /* TCO Base Address Register */
+/* TCO1 Control Register */
-#define TCO1_CNT	0x08 /* TCO1 Control Register */
+#define TCO1_CNT	0x68
 
 #define GEN_PMCON_1		0xa0
 #define GEN_PMCON_2		0xa2

src/southbridge/intel/i82801dx/lpc.c

@@ -4,6 +4,7 @@
 #include <arch/io.h>
 #include <arch/ioapic.h>
 #include <console/console.h>
+#include <cpu/x86/smm.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
@@ -162,6 +163,15 @@ static void i82801dx_rtc_init(struct device *dev)
 	pci_write_config8(dev, RTC_CONF, 0x04);
 }
 
+static void i82801dx_set_acpi_mode(struct device *dev)
+{
+	if (!acpi_is_wakeup_s3()) {
+		apm_control(APM_CNT_ACPI_DISABLE);
+	} else {
+		apm_control(APM_CNT_ACPI_ENABLE);
+	}
+}
+
 static void i82801dx_lpc_route_dma(struct device *dev, u8 mask)
 {
 	u16 reg16;
@@ -240,6 +250,8 @@ static void lpc_init(struct device *dev)
 	enable_hpet(dev);
 
 	setup_i8259();
+
+	i82801dx_set_acpi_mode(dev);
 }
 
 static void i82801dx_lpc_read_resources(struct device *dev)

src/southbridge/intel/i82801dx/smihandler.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/pmutil.h>
+#include "i82801dx.h"
+
+void southbridge_smi_monitor(void)
+{
+}
+
+void southbridge_finalize_all(void)
+{
+}