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trogdor: Add support for rev1 

This patch implements the pin changes needed for Trogdor rev1.
Unfortunately, coreboot has to get the EC and TPM SPI busses compiled
into Kconfig, so we cannot really build a single image that runs on both
revisions. Introduce a Kconfig to handle this instead.

Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Julius Werner 2020-02-06 16:44:40 -08:00
parent 8ad0c86da2
commit 561b8cc2e7
3 changed files with 10 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/mainboard/google/trogdor/Kconfig
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@ -4,6 +4,9 @@ config BOARD_GOOGLE_TROGDOR_COMMON # Umbrella option to be selected by variants
if BOARD_GOOGLE_TROGDOR_COMMON if BOARD_GOOGLE_TROGDOR_COMMON
config TROGDOR_REV0
def_bool y
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
select BOARD_ROMSIZE_KB_8192 select BOARD_ROMSIZE_KB_8192
@ -32,11 +35,13 @@ config MAINBOARD_DIR
config DRIVER_TPM_SPI_BUS config DRIVER_TPM_SPI_BUS
hex hex
default 0x6 default 0x6 if TROGDOR_REV0
default 0x0
config EC_GOOGLE_CHROMEEC_SPI_BUS config EC_GOOGLE_CHROMEEC_SPI_BUS
hex hex
default 0x0 default 0x0 if TROGDOR_REV0
default 0x6
########################################################## ##########################################################
#### Update below when adding a new derivative board. #### #### Update below when adding a new derivative board. ####

1
src/mainboard/google/trogdor/board.h
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@ -3,6 +3,7 @@
#ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ #ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_
#define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ #define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_
#include <boardid.h>
#include <gpio.h> #include <gpio.h>
#include <soc/gpio.h> #include <soc/gpio.h>

5
src/mainboard/google/trogdor/bootblock.c
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@ -2,12 +2,11 @@
#include <bootblock_common.h> #include <bootblock_common.h>
#include "board.h" #include "board.h"
#include <soc/qcom_qup_se.h>
#include <soc/qupv3_spi.h> #include <soc/qupv3_spi.h>
void bootblock_mainboard_init(void) void bootblock_mainboard_init(void)
{ {
setup_chromeos_gpios(); setup_chromeos_gpios();
qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */ qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz);
qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */ qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz);
} }