soc/intel/tigerlake: Add config option for S3 ACPI

Add Kconfig option `SOC_INTEL_TIGERLAKE_S3` which will adjust
the ACPI to not offer D3Cold when using S3.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/tigerlake/Kconfig

@@ -187,6 +187,12 @@ config SOC_INTEL_I2C_DEV_MAX
 	int
 	default 6
 
+config SOC_INTEL_TIGERLAKE_S3
+	bool
+	default n
+	help
+	  Select if using S3 instead of S0ix to disable D3Cold
+
 config SOC_INTEL_UART_DEV_MAX
 	int
 	default 3

src/soc/intel/tigerlake/acpi/tcss.asl

@@ -41,6 +41,12 @@
 
 Scope (\_SB)
 {
+#if CONFIG(SOC_INTEL_TIGERLAKE_S3)
+	Name (S0IX, 0)
+#else
+	Name (S0IX, 1)
+#endif
+
 	/* Device base address */
 	Method (BASE, 1)
 	{
@@ -673,6 +679,7 @@ Scope (\_SB.PCI0)
 		}
 	}
 
+	If (S0IX == 1) {
 		Method (TCON, 0)
 		{
 			/* Reset IOM D3 cold bit if it is in D3 cold now. */
@@ -783,6 +790,7 @@ Scope (\_SB.PCI0)
 				STAT = 0
 			}
 		}
+	} /* End: S0IX */
 
 	/*
 	 * TCSS xHCI device

src/soc/intel/tigerlake/acpi/tcss_dma.asl

@@ -27,25 +27,49 @@ Name (STAT, 0x1)  /* Variable to save power state 1 - D0, 0 - D3C */
 
 Method (_S0W, 0x0)
 {
-	Return (0x4)
+	If (S0IX == 1) {
+		Return (0x04)
+	} Else {
+		Return (0x03)
+	}
 }
 
+/*
+ * Get power resources that are dependent on this device for Operating System Power Management
+ * to put the device in the D0 device state
+ */
 Method (_PR0)
 {
+	If (S0IX == 1) {
 		If (DUID == 0) {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 		} Else {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
 		}
+	} Else {
+		If (DUID == 0) {
+			Return (Package() { \_SB.PCI0.TBT0 })
+		} Else {
+			Return (Package() { \_SB.PCI0.TBT1 })
+		}
+	}
 }
 
 Method (_PR3)
 {
+	If (S0IX == 1) {
 		If (DUID == 0) {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 		} Else {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
 		}
+	} Else {
+		If (DUID == 0) {
+			Return (Package() { \_SB.PCI0.TBT0 })
+		} Else {
+			Return (Package() { \_SB.PCI0.TBT1 })
+		}
+	}
 }
 
 /*
@@ -53,8 +77,8 @@ Method (_PR3)
  */
 Method (D3CX, 0, Serialized)
 {
-	DD3E = 0	/* Disable DMA RTD3 */
-	STAT = 0x1
+	DD3E = 0x00	/* Disable DMA RTD3 */
+	STAT = 0x01
 }
 
 /*
@@ -62,8 +86,8 @@ Method (D3CX, 0, Serialized)
  */
 Method (D3CE, 0, Serialized)
 {
-	DD3E = 1	/* Enable DMA RTD3 */
-	STAT = 0
+	DD3E = 0x01	/* Enable DMA RTD3 */
+	STAT = 0x00
 }
 
 /*
@@ -71,7 +95,6 @@ Method (D3CE, 0, Serialized)
  * TCSS D3 Cold and TBT RTD3 is only available when system power state is in S0.
  */
 Name (SD3C, 0)
-
 Method (_PS0, 0, Serialized)
 {
 }

src/soc/intel/tigerlake/acpi/tcss_pcierp.asl

@@ -267,25 +267,45 @@ Method (_PS3, 0, Serialized)
 
 Method (_S0W, 0x0, NotSerialized)
 {
+	If (S0IX == 1) {
 		Return (0x4)
+	} Else {
+		Return (0x3)
+	}
 }
 
 Method (_PR0)
 {
+	If (S0IX == 1) {
 		If ((TUID == 0) || (TUID == 1)) {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 		} Else {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
 		}
+	} Else {
+		If ((TUID == 0) || (TUID == 1)) {
+			Return (Package() { \_SB.PCI0.TBT0 })
+		} Else {
+			Return (Package() { \_SB.PCI0.TBT1 })
+		}
+	}
 }
 
 Method (_PR3)
 {
+	If (S0IX == 1) {
 		If ((TUID == 0) || (TUID == 1)) {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 })
 		} Else {
 			Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 })
 		}
+	} Else {
+		If ((TUID == 0) || (TUID == 1)) {
+			Return (Package() { \_SB.PCI0.TBT0 })
+		} Else {
+			Return (Package() { \_SB.PCI0.TBT1 })
+		}
+	}
 }
 
 /*

src/soc/intel/tigerlake/acpi/tcss_xhci.asl

@@ -30,7 +30,11 @@ Method (_PS3, 0, Serialized)
 
 Method (_S0W, 0x0, NotSerialized)
 {
+	If (S0IX == 1) {
 		Return (0x4)
+	} Else {
+		Return (0x3)
+	}
 }
 
 /*
@@ -39,6 +43,7 @@ Method (_S0W, 0x0, NotSerialized)
  */
 Name (SD3C, 0)
 
+If (S0IX == 1) {
 	Method (_PR0)
 	{
 		Return (Package () { \_SB.PCI0.D3C })
@@ -48,6 +53,7 @@ Method (_PR3)
 	{
 		Return (Package () { \_SB.PCI0.D3C })
 	}
+}
 
 /*
  * XHCI controller _DSM method