t132: bring up 64-bit denver core
The startup sequence for cpu0 is implemented while also providing a trampoline for transitioning to 64-bit mode because the denver cores on t132 come out of cold reset in 32-bit mode. Mainboard callbacks are provided for providing the board-specific bits of the bringup sequence. BUG=chrome-os-partner:29923 BRANCH=None TEST=Built and booted through ramstage. Original-Change-Id: I50755fb6b06db994af8667969d8493f214a70aae Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207263 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 17f09bf4bdb43986c19067ca8fd65d4c5365a7c6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I14d99c24dd6e29a4584c8c548c4b26c92b6ade97 Reviewed-on: http://review.coreboot.org/8586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Aaron Durbin
Marc Jones
parent
1b770fb4b5
commit
5626d8f59a
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@ -33,6 +33,7 @@ bootblock-y += pmic.c
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bootblock-y += reset.c
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romstage-y += reset.c
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romstage-y += romstage.c
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romstage-y += sdram_configs.c
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ramstage-y += mainboard.c
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <soc/romstage.h>
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void mainboard_configure_pmc(void)
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{
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}
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void mainboard_enable_vdd_cpu(void)
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{
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/* VDD_CPU is already enabled in bootblock. */
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}
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@ -27,6 +27,7 @@ romstage-y += i2c.c
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romstage-y += dma.c
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romstage-y += monotonic_timer.c
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romstage-y += romstage.c
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romstage-y += power.c
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romstage-y += sdram.c
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romstage-y += sdram_lp0.c
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romstage-y += ../tegra/gpio.c
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@ -23,11 +23,15 @@
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#include <cbfs.h>
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#include <timer.h>
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#include <soc/addressmap.h>
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#include <soc/romstage.h>
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#include "clk_rst.h"
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#include "ccplex.h"
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#include "flow.h"
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#include "mc.h"
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#include "pmc.h"
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#include "power.h"
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#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100)
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#define CLK_RST_REGS (void *)(uintptr_t)(TEGRA_CLK_RST_BASE)
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#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE)
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#define MTS_FILE_NAME "mts"
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@ -105,3 +109,131 @@ int ccplex_load_mts(void)
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return ccplex_start();
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}
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static void enable_cpu_clocks(void)
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{
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struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS;
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uint32_t reg;
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reg = read32(&clk_rst->clk_enb_l_set);
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reg |= CLK_ENB_CPU;
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write32(reg, &clk_rst->clk_enb_l_set);
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reg = read32(&clk_rst->clk_enb_v_set);
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reg |= SET_CLK_ENB_CPUG_ENABLE | SET_CLK_ENB_CPULP_ENABLE;
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write32(reg, &clk_rst->clk_enb_v_set);
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}
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static void enable_cpu_power_partitions(void)
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{
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/* Bring up fast cluster, non-CPU, CPU0, and CPU1 partitions. */
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power_ungate_partition(POWER_PARTID_CRAIL);
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power_ungate_partition(POWER_PARTID_C0NC);
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power_ungate_partition(POWER_PARTID_CE0);
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power_ungate_partition(POWER_PARTID_CE1);
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}
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static void request_ram_repair(void)
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{
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struct flow_ctlr * const flow = (void *)(uintptr_t)TEGRA_FLOW_BASE;
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const uint32_t req = 1 << 0;
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const uint32_t sts = 1 << 1;
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uint32_t reg;
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struct mono_time t1, t2;
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printk(BIOS_DEBUG, "Requesting RAM repair.\n");
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reg = read32(&flow->ram_repair);
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reg |= req;
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write32(reg, &flow->ram_repair);
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timer_monotonic_get(&t1);
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while ((read32(&flow->ram_repair) & sts) != sts);
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timer_monotonic_get(&t2);
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printk(BIOS_DEBUG, "RAM repair complete in %ld usecs.\n",
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mono_time_diff_microseconds(&t1, &t2));
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}
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void ccplex_cpu_prepare(void)
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{
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enable_cpu_clocks();
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enable_cpu_power_partitions();
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mainboard_configure_pmc();
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mainboard_enable_vdd_cpu();
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request_ram_repair();
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}
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static void start_cpu0(void)
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{
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struct clk_rst_ctlr * const clk_rst = CLK_RST_REGS;
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/* Clear fast CPU partition reset. */
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write32(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr);
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/* Clear reset of CPU0 components. */
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write32(CRC_RST_CPUG_CLR_CPU0 |
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CRC_RST_CPUG_CLR_DBG0 |
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CRC_RST_CPUG_CLR_CORE0 |
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CRC_RST_CPUG_CLR_CX0 |
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CRC_RST_CPUG_CLR_L2 |
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CRC_RST_CPUG_CLR_PDBG, &clk_rst->rst_cpug_cmplx_clr);
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}
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/*
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* The Denver cores come up in aarch32 mode. In order to transition to
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* 64-bit mode a write to the RMR (reset mangement register) with the
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* AA64 bit (0) set while setting RR (reset request bit 1).
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*/
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static const uint32_t aarch32to64[] = {
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0xe3a00003, /* mov r0, #3 */
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0xee0c0f50, /* mcr 15, 0, r0, cr12, cr0, {2} */
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};
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static void load_aarch64_trampoline(void *addr)
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{
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const size_t trampoline_size = sizeof(aarch32to64);
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const void * const trampoline = &aarch32to64[0];
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/* Copy trampoline into ram. */
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memcpy(addr, trampoline, trampoline_size);
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}
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void ccplex_cpu_start(void *entry_addr)
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{
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struct tegra_pmc_regs * const pmc = PMC_REGS;
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void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
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void *trampoline;
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uint32_t entry_point;
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/*
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* Just place the trampoline at the MTS_LOAD_ADDRESS. This assumes
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* the program to run doesn't overlap this address.
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*/
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const uint32_t trampoline_addr = MTS_LOAD_ADDRESS;
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trampoline = (void *)(uintptr_t)trampoline_addr;
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/* The arm entry points have bit 0 set if thumb code. Mask that off. */
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entry_point = (uint32_t)(uintptr_t)entry_addr;
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load_aarch64_trampoline(trampoline);
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/* Warm reset vector is pulled from the PMC scratch registers. */
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write32(entry_point, &pmc->secure_scratch34);
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write32(0, &pmc->secure_scratch35);
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printk(BIOS_DEBUG, "Starting CPU0 @ %p trampolining to %08x.\n",
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trampoline, entry_point);
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/*
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* The Denver cores start in 32-bit mode. Therefore a trampoline
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* is needed to get into 64-bit mode. Point the cold reset vector
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* to the trampoline location.
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*/
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write32(trampoline_addr, evp_cpu_reset_vector);
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start_cpu0();
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}
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@ -22,7 +22,13 @@
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#define MTS_LOAD_ADDRESS 0x82000000
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/* Prepare the clocks and rails to start the cpu. */
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void ccplex_cpu_prepare(void);
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/* Loads the MTS microcode. Return 0 on success, < 0 on error. */
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int ccplex_load_mts(void);
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/* Start cpu0 and have it start executing at entry_addr */
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void ccplex_cpu_start(void *entry_addr);
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#endif /* __SOC_NVIDIA_TEGRA132_CCPLEX_H__ */
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
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#define __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__
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void mainboard_configure_pmc(void);
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void mainboard_enable_vdd_cpu(void);
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#endif /* __SOC_NVIDIA_TEGRA132_SOC_ROMSTAGE_H__ */
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@ -0,0 +1,57 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include "pmc.h"
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#include "power.h"
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static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE;
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static int partition_powered(int id)
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{
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return read32(&pmc->pwrgate_status) & (0x1 << id);
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}
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void power_ungate_partition(uint32_t id)
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{
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printk(BIOS_INFO, "Ungating power partition %d.\n", id);
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if (!partition_powered(id)) {
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uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle);
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pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
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pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
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pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
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write32(pwrgate_toggle, &pmc->pwrgate_toggle);
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/* Wait for the request to be accepted. */
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while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
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;
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printk(BIOS_DEBUG, "Power gate toggle request accepted.\n");
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/* Wait for the partition to be powered. */
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while (!partition_powered(id))
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;
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}
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printk(BIOS_INFO, "Ungated power partition %d.\n", id);
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}
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@ -20,10 +20,8 @@
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#ifndef __SOC_NVIDIA_TEGRA132_POWER_H__
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#define __SOC_NVIDIA_TEGRA132_POWER_H__
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// This function does not enable the external power to the rail, it enables
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// the rail itself internal to the SOC.
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void power_enable_cpu_rail(void);
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#include "pmc.h"
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void power_ungate_cpu(void);
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void power_ungate_partition(uint32_t id);
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#endif /* __SOC_NVIDIA_TEGRA132_POWER_H__ */
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@ -39,12 +39,16 @@ void romstage(void)
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sdram_init(get_sdram_config());
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printk(BIOS_INFO, "T132 romstage: sdram_init done\n");
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ccplex_cpu_prepare();
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printk(BIOS_INFO, "T132 romstage: cpu prepare done\n");
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ccplex_load_mts();
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printk(BIOS_INFO, "T132 romstage: MTS loading done\n");
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while (1);
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entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
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CONFIG_CBFS_PREFIX "/ramstage");
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stage_exit(entry);
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ccplex_cpu_start(entry);
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while (1);
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}
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