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mb/siemens/mc_apl3: Enable LPSS UART 1 

By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.

Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2019-07-11 14:31:34 +02:00 committed by Martin Roth
parent b14f3b8b0b
commit 56352e1f80
1 changed files with 3 additions and 2 deletions
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5
src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
View File

@ -325,8 +325,9 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */
PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */
PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */
PAD_CFG_GPI(GPIO_42, UP_20K, DEEP), /* LPSS_UART1_RXD - unused */
PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */
PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */
/* LPSS_UART1_TXD */
PAD_CFG_NF_IOSSTATE(GPIO_43, NATIVE, DEEP, NF1, Tx1RxDCRx0),
PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */
PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */
PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), /* LPSS_UART2_RXD */