diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl
index e044f04822..f19ac6c125 100644
--- a/src/southbridge/intel/common/acpi/platform.asl
+++ b/src/southbridge/intel/common/acpi/platform.asl
@@ -11,16 +11,6 @@ Field (APMP, ByteAcc, NoLock, Preserve)
 
 #include <arch/x86/acpi/post.asl>
 
-#if CONFIG(ACPI_SOC_NVS)
-/* SMI I/O Trap */
-Method(TRAP, 1, Serialized)
-{
-	SMIF = Arg0	// SMI Function
-	TRP0 = 0		// Generate trap
-	Return (SMIF)		// Return value of SMI handler
-}
-#endif /* ACPI_SOC_NVS */
-
 Method(GOS, 0)
 {
 	/* Determine the Operating System and save the value in OSYS.
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index 6c9c9694f9..f30d3be052 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -15,6 +15,14 @@ Scope(\)
 		TRP0, 8		// IO-Trap at 0x808
 	}
 
+	/* SMI I/O Trap */
+	Method(TRAP, 1, Serialized)
+	{
+		SMIF = Arg0	// SMI Function
+		TRP0 = 0	// Generate trap
+		Return (SMIF)	// Return value of SMI handler
+	}
+
 	// ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
 	OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
 	Field(PMIO, ByteAcc, NoLock, Preserve)