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binaryPI: Drop CAR teardown without POSTCAR_STAGE 

The remaining (active) binaryPI boards moved away from
BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now.

As the cache_as_ram.S is also used with AGESA, this slightly
reduces the codesize there for romstage and postcar as well.

This commit is actually a revert for the vendorcode parts,
AMD originally shipped the codes using 'invd' for the CAR
teardown, but these were changed for coreboot due the
convoluted teardown that used to happen with non-empty stack.

Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2017-09-07 22:13:10 +03:00
parent 46f04cbb49
commit 56397364c9
6 changed files with 45 additions and 139 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/amd/agesa/Makefile.inc
View File

@ -20,7 +20,7 @@ romstage-y += state_machine.c
ramstage-y += state_machine.c
cpu_incs-y += $(src)/drivers/amd/agesa/cache_as_ram.S
postcar-y += cache_as_ram.S
postcar-y += exit_car.S
romstage-y += def_callouts.c
romstage-y += eventlog.c

58
src/drivers/amd/agesa/cache_as_ram.S
View File

@ -27,7 +27,6 @@
.code32
.globl _cache_as_ram_setup, _cache_as_ram_setup_end
.globl chipset_teardown_car
_cache_as_ram_setup:
@ -105,66 +104,11 @@ _cache_as_ram_setup:
pushl %eax
call romstage_main
#if CONFIG(POSTCAR_STAGE)
/* We do not return. Execution continues with run_postcar_phase()
* calling to chipset_teardown_car below.
*/
jmp postcar_entry_failure
chipset_teardown_car:
/*
* Retrieve return address from stack as it will get trashed below if
* execution is utilizing the cache-as-ram stack.
*/
pop %esp
#else
movl %eax, %esp
/* Register %esp is new stacktop for remaining of romstage. */
#endif
/* Disable cache */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
/* Register %esp is preserved in AMD_DISABLE_STACK. */
AMD_DISABLE_STACK
#if CONFIG(POSTCAR_STAGE)
jmp *%esp
#else
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff, %eax
movl %eax, %cr0
call romstage_after_car
#endif
/* Should never see this postcode */
post_code(0xaf)
post_code(0xae)
stop:
hlt
jmp stop
/* These are here for linking purposes. */
.weak early_all_cores, romstage_main
early_all_cores:
romstage_main:
postcar_entry_failure:
/* Should never see this postcode */
post_code(0xae)
jmp stop
_cache_as_ram_setup_end:

37
src/drivers/amd/agesa/exit_car.S Normal file
View File

@ -0,0 +1,37 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2011 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <gcccar.inc>
#include <cpu/x86/cache.h>
.code32
.globl chipset_teardown_car
chipset_teardown_car:
pop %esp
/* Disable cache */
movl %cr0, %eax
orl $CR0_CacheDisable, %eax
movl %eax, %cr0
AMD_DISABLE_STACK
/* enable cache */
movl %cr0, %eax
andl $(~(CR0_CD | CR0_NW)), %eax
movl %eax, %cr0
jmp *%esp

29
src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
View File

@ -696,13 +696,6 @@ fam15_enable_stack_hook_exit:
* Return any family specific controls to their 'standard'
* settings for using cache with main memory.
*
* Note: Customized for coreboot:
* A wbinvd is used to send cache to memory. The existing stack is preserved
* at its original location and additional information is preserved (e.g.
* coreboot CAR globals, heap structures, etc.). This implementation should
* NOT be used with S3 resume IF the stack/cache area is not reserved and
* over system memory.
*
* Inputs:
* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
* Outputs:
@ -911,16 +904,7 @@ fam15_disable_stack_remote_read_exit:
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
#--------------------------------------------------------------------------
# Send cache to memory. Preserve stack and coreboot CAR globals.
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
#if !CONFIG(POSTCAR_STAGE)
wbinvd
#else
invd
#endif
#.if (bh == 01h) || (bh == 03h) ; Is this TN or KV?
cmp $01, %bh
@ -1563,17 +1547,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is
.endm
/*****************************************************************************
* AMD_DISABLE_STACK: Implementation is modified for coreboot from
* the original AMD intent. A WBINVD is used in the HOOK
* to send dirty cache contents to DRAM backing before
* disabling cache-as-ram. This is not safe for S3 resume.
*
* todo:
* * rework PI/AGESA source to set DRAM to UC to send
* writes directly to memory
* * move DCACHE_BASE or use postcar stage for teardown
* to eliminate car_migrated problem that will occur
* after wbinvd is changed back to invd
* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
* should only be executed on the BSP
*
* In:
* none

29
src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
View File

@ -401,13 +401,6 @@ fam15_enable_stack_hook_exit:
* Return any family specific controls to their 'standard'
* settings for using cache with main memory.
*
* Note: Customized for coreboot:
* A wbinvd is used to send cache to memory. The existing stack is preserved
* at its original location and additional information is preserved (e.g.
* coreboot CAR globals, heap structures, etc.). This implementation should
* NOT be used with S3 resume IF the stack/cache area is not reserved and
* over system memory.
*
* Inputs:
* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
* Outputs:
@ -646,16 +639,7 @@ fam15_disable_stack_remote_read_exit:
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
#--------------------------------------------------------------------------
# Send cache to memory. Preserve stack and coreboot CAR globals.
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
#if !CONFIG(POSTCAR_STAGE)
wbinvd
#else
invd
#endif
# #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
# cmp $01, %bh
@ -1302,17 +1286,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is
.endm
/*****************************************************************************
* AMD_DISABLE_STACK: Implementation is modified for coreboot from
* the original AMD intent. A WBINVD is used in the HOOK
* to send dirty cache contents to DRAM backing before
* disabling cache-as-ram. This is not safe for S3 resume.
*
* todo:
* * rework PI/AGESA source to set DRAM to UC to send
* writes directly to memory
* * move DCACHE_BASE or use postcar stage for teardown
* to eliminate car_migrated problem that will occur
* after wbinvd is changed back to invd
* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
* should only be executed on the BSP
*
* In:
* none

29
src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
View File

@ -383,13 +383,6 @@ fam16_enable_stack_hook_exit:
; Return any family specific controls to their 'standard'
; settings for using cache with main memory.
;
; Note: Customized for coreboot:
; A wbinvd is used to send cache to memory. The existing stack is preserved
; at its original location and additional information is preserved (e.g.
; coreboot CAR globals, heap structures, etc.). This implementation should
; NOT be used with S3 resume IF the stack/cache area is not reserved and
; over system memory.
;
; Inputs:
; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core#
; Outputs:
@ -610,16 +603,7 @@ fam16_disable_stack_remote_read_exit:
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
#--------------------------------------------------------------------------
# Send cache to memory. Preserve stack and coreboot CAR globals.
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
#if !CONFIG(POSTCAR_STAGE)
wbinvd
#else
invd
#endif
#Do Standard Family 16 work
mov $HWCR, %ecx # MSR:C001_0015h
@ -1276,17 +1260,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is
.endm
/*****************************************************************************
* AMD_DISABLE_STACK: Implementation is modified for coreboot from
* the original AMD intent. A WBINVD is used in the HOOK
* to send dirty cache contents to DRAM backing before
* disabling cache-as-ram. This is not safe for S3 resume.
*
* todo:
* * rework PI/AGESA source to set DRAM to UC to send
* writes directly to memory
* * move DCACHE_BASE or use postcar stage for teardown
* to eliminate car_migrated problem that will occur
* after wbinvd is changed back to invd
* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
* should only be executed on the BSP
*
* In:
* none