diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 6c6e5be598..75a1b1a363 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -187,26 +187,14 @@ static void sata_init(struct device *dev)
 			printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n");
 		}
 
-		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
-				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
-				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
-				IDE_SITRE | IDE_ISP_3_CLOCKS |
-				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+		/* Enable I/O decoding */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
 
-		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
-
-		/* Set IDE I/O Configuration */
-		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-		pci_write_config32(dev, IDE_CONFIG, reg32);
-
-		/* Port enable */
+		/* Port enable + OOB retry mode */
 		reg16 = pci_read_config16(dev, 0x92);
 		reg16 &= ~0x3f;
-		reg16 |= config->sata_port_map;
+		reg16 |= config->sata_port_map | 0x8000;
 		pci_write_config16(dev, 0x92, reg16);
 
 		/* SATA Initialization register */