soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden

Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/alderlake/chipset.cb

@@ -248,7 +248,7 @@ chip soc/intel/alderlake
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias pch_espi on end
-		device pci 1f.1 alias p2sb off end
+		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
 		device pci 1f.4 alias smbus off end

src/soc/intel/alderlake/chipset_pch_s.cb

@@ -242,7 +242,7 @@ chip soc/intel/alderlake
 		device pci 1e.2 alias gspi0 off end
 		device pci 1e.3 alias gspi1 off end
 		device pci 1f.0 alias pch_espi on end
-		device pci 1f.1 alias p2sb off end
+		device pci 1f.1 alias p2sb hidden end
 		device pci 1f.2 alias pmc hidden end
 		device pci 1f.3 alias hda off end
 		device pci 1f.4 alias smbus off end