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AGESA f15tn: Fix GPP ports resume 

The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(),
which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink()
looks into CMOS to figure out what ports to just force to Gen1 or
Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP
init is executed. There is a problem that nobody sets properly the
PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving()
thinks the GPP port is not enabled and shut downs it.

The best fix would be also to remove the CMOS dependency which
might be some left over, because AGESA does not use CMOS much for
anything else. There could be also some way how to pass the GPP state
structure from romstage to ramstage possibly via hudson/resume.c
but I don't know how to do that. Similar problem is that the "late"
stage of init again "forgets" the PortDetected state.

This fix fixes the resume issue on Asus F2A85-M. With this patch applied
both GPP ports (used as PCIe x1 and internal ethernet) are working again
after resume.

Change-Id: Idaf609043abb09441c6790504d66d23e0637588f
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4671
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Rudolf Marek 2014-01-12 00:23:30 +01:00
parent d69757bd4e
commit 566b4f008f
2 changed files with 20 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c
View File

@ -65,10 +65,26 @@ FchInitEnvGpp (
{ {
FCH_DATA_BLOCK *LocalCfgPtr; FCH_DATA_BLOCK *LocalCfgPtr;
AMD_CONFIG_PARAMS *StdHeader; AMD_CONFIG_PARAMS *StdHeader;
UINT8 GppS3Data;
UINT8 PortId;
LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
StdHeader = LocalCfgPtr->StdHeader; StdHeader = LocalCfgPtr->StdHeader;
/*
* The romstage will force link, but re-read the GPP params from CMOS,
* otherwise the late init will powerdown all ports including
* those which were just taken out of S3
*/
if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) {
ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data);
for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) {
if ( GppS3Data & (1 << (PortId + 4))) {
LocalCfgPtr->Gpp.PortCfg[PortId].PortDetected = TRUE;
}
}
}
if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) { if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) {
ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader); ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader);
FchStall (5000, StdHeader); FchStall (5000, StdHeader);

5
src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c
View File

@ -281,6 +281,9 @@ FchInitLateGpp (
RwAlink (0x310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader); RwAlink (0x310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader);
RwAlink (FCH_RCINDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader); RwAlink (FCH_RCINDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader);
} }
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data);
if (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3) {
RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data);
}
} }