From 5671787b9e36ca80b39dcbbfb0307e3c697c8e20 Mon Sep 17 00:00:00 2001 From: Rudolf Marek Date: Sat, 15 Mar 2008 00:26:50 +0000 Subject: [PATCH] Following patch extends the ROM decoding to last 1MB, allowing to use larger flashes such as SST49LF080A: 1024K x8 (8 Mbit) Tested on my system, the flash is found and if I use coreboot in second half it works too. Signed-off-by: Rudolf Marek Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c | 2 ++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c | 15 +++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c index 796b87f581..58dce4dd05 100644 --- a/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c +++ b/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c @@ -192,6 +192,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); + enable_rom_decode(); print_info("now booting... fallback\r\n"); @@ -259,6 +260,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) w83627ehg_enable_serial(SERIAL_DEV, TTYS0_BASE); uart_init(); console_init(); + enable_rom_decode(); print_info("now booting... real_main\r\n"); diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c index 9116e46dbd..5e62f39e4d 100644 --- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c +++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c @@ -212,3 +212,18 @@ void smbus_fixup(const struct mem_controller *ctrl) else PRINT_DEBUG("Done\r\n"); } + +void enable_rom_decode(void) +{ + device_t dev; + + /* Bus Control and Power Management */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + + if (dev == PCI_DEV_INVALID) + die("SB not found\r\n"); + + /* ROM decode last 1MB FFC00000 - FFFFFFFF */ + pci_write_config8(dev, 0x41, 0x7f); +}