mb/siemens/mc_apl1/var/mc_apl5: Enable early POST

Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.

BUG=none
TEST=Boot on mc_apl5 and observe that POST codes are
displayed before DRAM training.

Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/siemens/mc_apl1/variants/mc_apl5/Kconfig

@@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select RX6110SA_DISABLE_ACPI
 	select DRIVER_SIEMENS_NC_FPGA
 	select NC_FPGA_NOTIFY_CB_READY
+	select NC_FPGA_POST_CODE
 	select SOC_INTEL_DISABLE_POWER_LIMITS
 	select MAINBOARD_HAS_TPM2
 	select MEMORY_MAPPED_TPM
@@ -30,4 +31,19 @@ config VBOOT
 config FMDFILE
 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/mc_apl_vboot.fmd"
 
+config EARLY_PCI_BRIDGE_DEVICE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x13
+
+config EARLY_PCI_BRIDGE_FUNCTION
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0x3
+
+config EARLY_PCI_MMIO_BASE
+	hex
+	depends on NC_FPGA_POST_CODE
+	default 0xfe800000
+
 endif # BOARD_SIEMENS_MC_APL5