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soc/intel/cannonlake: Drop unused LPC BIOS Control macro 

This patch drops unused LPC BIOS control macros.

BUG=b:211954778
TEST=Able to build and boot google/hatch.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib309c6bd0f27115357f8e62200808764748f51a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2022-04-18 11:46:39 +05:30 committed by Felix Held
parent 86f4352a47
commit 5685cbb958
1 changed files with 0 additions and 4 deletions
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4
src/soc/intel/cannonlake/include/soc/lpc.h
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@ -24,10 +24,6 @@
#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
#define LGMR 0x98 /* LPC Generic Memory Range */ #define LGMR 0x98 /* LPC Generic Memory Range */
#define BIOS_CNTL 0xdc
#define LPC_BC_BILD (1 << 7) /* BILD */
#define LPC_BC_LE (1 << 1) /* LE */
#define LPC_BC_EISS (1 << 5) /* EISS */
#define PCCTL 0xE0 /* PCI Clock Control */ #define PCCTL 0xE0 /* PCI Clock Control */
#define CLKRUN_EN (1 << 0) #define CLKRUN_EN (1 << 0)