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soc/intel/common: lpc/espi: fix wrong lock bit 

This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance
with doc#332691-003EN and doc#334819-001.

Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Michael Niewöhner 2019-10-17 16:32:24 +02:00 committed by Patrick Georgi
parent fb57d7c549
commit 569887a640
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/common/block/lpc/lpc_def.h
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@ -37,7 +37,7 @@
#define LPC_LGMR_WINDOW_SIZE (64 * KiB) #define LPC_LGMR_WINDOW_SIZE (64 * KiB)
#define LPC_BIOS_CNTL 0xdc #define LPC_BIOS_CNTL 0xdc
#define LPC_BC_BILD (1 << 7) /* BILD */ #define LPC_BC_BILD (1 << 7) /* BILD */
#define LPC_BC_LE (1 << 2) /* LE */ #define LPC_BC_LE (1 << 1) /* LE */
#define LPC_BC_EISS (1 << 5) /* EISS */ #define LPC_BC_EISS (1 << 5) /* EISS */
#define LPC_PCCTL 0xE0 /* PCI Clock Control */ #define LPC_PCCTL 0xE0 /* PCI Clock Control */
#define LPC_PCCTL_CLKRUN_EN (1 << 0) #define LPC_PCCTL_CLKRUN_EN (1 << 0)