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southbridge/amd/sr5650: Use correct PCI configuration block offset 

Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12049
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Timothy Pearson 2015-08-14 02:50:44 -05:00 committed by Martin Roth
parent 259549678b
commit 56c8ef9a91
1 changed files with 2 additions and 2 deletions
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4
src/southbridge/amd/sr5650/acpi/sr5650.asl
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@ -15,8 +15,8 @@
*/
Scope(\) {
Name(PCBA, 0xE0000000) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* PIC IRQ mapping registers, C00h-C01h */
OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)