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soc/intel/quark: Set temporary I2C base address 

Set a temporary I2C base address during romstage.

TEST=Build and run on Galileo Gen2

Change-Id: I4b427c66a4e7e6d30cc611d4d3c40bb0ea36066d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15006
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-05-30 14:16:10 -07:00 committed by Leroy P Leahy
parent ca65bb7b4e
commit 56c99f2850
2 changed files with 4 additions and 2 deletions
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3
src/soc/intel/quark/include/soc/iomap.h
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@ -25,7 +25,8 @@
#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE #define UART_BASE_ADDRESS CONFIG_TTYS0_BASE
/* I2C/GPIO Controller */ /* I2C/GPIO Controller */
#define I2C_GPIO_BASE_ADDRESS 0xa0020000 #define I2C_BASE_ADDRESS 0xa0020000
#define GPIO_BASE_ADDRESS 0xa0021000
/* /*
* I/O port address space * I/O port address space

3
src/soc/intel/quark/romstage/romstage.c
View File

@ -52,7 +52,8 @@ static const struct reg_script legacy_gpio_init[] = {
static const struct reg_script i2c_gpio_controller_init[] = { static const struct reg_script i2c_gpio_controller_init[] = {
/* Temporarily enable the GPIO controller */ /* Temporarily enable the GPIO controller */
REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, I2C_GPIO_BASE_ADDRESS), REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY), REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
REG_SCRIPT_END REG_SCRIPT_END
}; };