This patch adds automatic fan control for the CPU fan on the m57sli
board. This is done via the ec_init routine in a source file in the mainboard/gigabyte/m57sli directory. A Config variable 'HAVE_FANCTL' has been added to notify superio.c to get the ec_init externally. I (Ward) have tested this on the PLCC and the SOIC/SPI version of this board. It works. Signed-off-by: Ronald Hoogenboom <hoogenboom30@zonnet.nl> Acked-by: Ward Vandewege <ward@gnu.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -861,6 +861,11 @@ end
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# Misc device options
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###############################################
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define HAVE_FANCTL
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default 0
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export used
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comment "Include board specific FAN control initialization"
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end
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define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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default 0
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export used
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@ -206,6 +206,10 @@ else
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end
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end
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if HAVE_FANCTL
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object fanctl.o
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end
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##
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## Setup RAM
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##
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@ -115,6 +115,7 @@ uses WAIT_BEFORE_CPUS_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses HAVE_FANCTL
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###
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### Build options
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###
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@ -139,6 +140,11 @@ default FAILOVER_SIZE=0x01000
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#more 1M for pgtbl
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default CONFIG_LB_MEM_TOPK=2048
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##
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## Set-up automatic fan control
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##
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default HAVE_FANCTL=1
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##
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## Build code for the fallback boot
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##
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@ -0,0 +1,57 @@
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#include <arch/io.h>
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static void write_index(uint16_t port_base, uint8_t reg, uint8_t value)
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{
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outb(reg, port_base);
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outb(value, port_base + 1);
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}
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static const struct {
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uint8_t index, value;
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} sequence[]= {
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/* Set FAN_CTL control register (0x14) polarity to high, and
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activate fans 1, 2 and 3. */
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{ 0x14, 0x87},
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/* set the correct sensor types 1,2 thermistor; 3 diode */
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{ 0x51, 0x1c},
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/* set the 'zero' voltage for diode type sensor */
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{ 0x5c, 0x80},
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// { 0x56, 0xe5},
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// { 0x57, 0xe5},
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{ 0x59, 0xe5},
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{ 0x5c, 0x00},
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/* fan1 (controlled by temp3) control parameters */
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/* fan off limit */
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{ 0x60, 0xff},
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/* fan start limit */
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{ 0x61, 0x14},
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/* ???? */
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// { 0x62, 0x00},
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/* start PWM */
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{ 0x63, 0x27},
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/* smooth and slope PWM */
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{ 0x64, 0x90},
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/* direct-down and interval */
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{ 0x65, 0x03},
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/* fan1 auto controlled by temp3 */
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{ 0x15, 0x82},
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/* fan2 soft controlled, max speed */
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{ 0x16, 0x7f},
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/* fan3 soft controlled, 75% speed */
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{ 0x17, 0x60},
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/* all fans enable, fan1 ctl smart */
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{ 0x13, 0x71}
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};
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#define ARRAYSIZE(x) sizeof x/sizeof *x
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/*
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* Called from superio.c
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*/
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void init_ec(uint16_t base)
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{
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int i;
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for (i=0; i<ARRAYSIZE(sequence); i++) {
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write_index(base, sequence[i].index, sequence[i].value);
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}
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}
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@ -62,6 +62,9 @@ static uint8_t pnp_read_index(uint16_t port_base, uint8_t reg)
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return inb(port_base + 1);
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}
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#ifdef HAVE_FANCTL
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extern void init_ec(uint16_t base);
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#else
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static void init_ec(uint16_t base)
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{
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uint8_t value;
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@ -77,6 +80,7 @@ static void init_ec(uint16_t base)
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printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
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base + 0x14, value | 0x87);
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}
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#endif
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static void it8716f_init(device_t dev)
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{
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