soc/amd/common/block/acpi/cpu_power_state: use pstate_msr union
Use the pstate_msr union in get_pstate_info to check if the P state enable bit is set. Also drop the now unused PSTATE_DEF_HI_ENABLE_SHIFT and PSTATE_DEF_HI_ENABLE_MASK definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I79119e09af79a4bb680a18e93b4a61a049f0080e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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2 changed files with 6 additions and 6 deletions
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@ -41,8 +41,6 @@
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#define PS_STS_REG 0xC0010063
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#define PSTATE_0_MSR 0xC0010064
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#define PSTATE_MSR(pstate) (PSTATE_0_MSR + (pstate))
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#define PSTATE_DEF_HI_ENABLE_SHIFT 31
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#define PSTATE_DEF_HI_ENABLE_MASK (0x1 << PSTATE_DEF_HI_ENABLE_SHIFT)
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#define MSR_PATCH_LOADER 0xC0010020
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@ -7,6 +7,7 @@
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#include <console/console.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/msr.h>
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#include <soc/msr.h>
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#include <types.h>
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/*
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@ -16,8 +17,9 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
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struct acpi_xpss_sw_pstate *pstate_xpss_values)
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{
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msr_t pstate_def;
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union pstate_msr pstate_reg;
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size_t pstate_count, pstate;
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uint32_t pstate_enable, max_pstate;
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uint32_t max_pstate;
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pstate_count = 0;
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max_pstate = (rdmsr(PS_LIM_REG).lo & PS_LIM_MAX_VAL_MASK) >> PS_MAX_VAL_SHFT;
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@ -25,9 +27,9 @@ static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
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for (pstate = 0; pstate <= max_pstate; pstate++) {
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pstate_def = rdmsr(PSTATE_MSR(pstate));
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pstate_enable = (pstate_def.hi & PSTATE_DEF_HI_ENABLE_MASK)
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>> PSTATE_DEF_HI_ENABLE_SHIFT;
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if (!pstate_enable)
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pstate_reg.raw = pstate_def.raw;
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if (!pstate_reg.pstate_en)
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continue;
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pstate_values[pstate_count].core_freq = get_pstate_core_freq(pstate_def);
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