soc/intel/common: use common Intel ACPI hardware definitions
Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: I40560b2a65a0cff6808ccdec80e0339786bf8908 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15668 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -137,14 +137,14 @@ void southbridge_smi_sleep(const struct smm_save_state_ops *save_state_ops)
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/* Figure out SLP_TYP */
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reg32 = inl(ACPI_PMIO_BASE + PM1_CNT);
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printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
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slp_typ = (reg32 >> 10) & 7;
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slp_typ = acpi_sleep_from_pm1(reg32);
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/* Do any mainboard sleep handling */
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mainboard_smi_sleep(slp_typ-2);
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mainboard_smi_sleep(slp_typ);
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/* Log S3, S4, and S5 entry */
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if (slp_typ >= 5 && IS_ENABLED(CONFIG_ELOG_GSMI))
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elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
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if (slp_typ >= ACPI_S3 && IS_ENABLED(CONFIG_ELOG_GSMI))
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elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
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/* Clear pending GPE events */
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clear_gpe_status();
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@ -152,19 +152,19 @@ void southbridge_smi_sleep(const struct smm_save_state_ops *save_state_ops)
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/* Next, do the deed. */
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switch (slp_typ) {
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case SLP_TYP_S0:
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case ACPI_S0:
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printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
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break;
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case SLP_TYP_S3:
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case ACPI_S3:
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printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
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/* Invalidate the cache before going to S3 */
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wbinvd();
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break;
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case SLP_TYP_S4:
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case ACPI_S4:
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printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
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break;
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case SLP_TYP_S5:
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case ACPI_S5:
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printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
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/* Disable all GPE */
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@ -188,7 +188,7 @@ void southbridge_smi_sleep(const struct smm_save_state_ops *save_state_ops)
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enable_pm1_control(SLP_EN);
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/* Make sure to stop executing code here for S3/S4/S5 */
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if (slp_typ > 1)
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if (slp_typ >= ACPI_S3)
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hlt();
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/*
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