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soc/intel/broadwell: Use the common cpu/intel/car romstage entry

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The only functional difference is the use of stack guards.

Change-Id: I95645271e0d93a97f544a1cc4e9a4320738e6a20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans 2019-05-12 14:01:13 +02:00 committed by Patrick Georgi
parent 724c66c88f
commit 56f768774a
2 changed files with 5 additions and 19 deletions
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1
src/soc/intel/broadwell/romstage/Makefile.inc
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@ -1,5 +1,6 @@
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += cpu.c romstage-y += cpu.c
romstage-y += pch.c romstage-y += pch.c
romstage-y += power_state.c romstage-y += power_state.c

23
src/soc/intel/broadwell/romstage/romstage.c
View file

@ -21,6 +21,7 @@
#include <bootmode.h> #include <bootmode.h>
#include <cbmem.h> #include <cbmem.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/romstage.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <elog.h> #include <elog.h>
#include <program_loading.h> #include <program_loading.h>
@ -39,7 +40,7 @@
/* platform_enter_postcar() determines the stack to use after /* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use, * cache-as-ram is torn down as well as the MTRR settings to use,
* and continues execution in postcar stage. */ * and continues execution in postcar stage. */
static void platform_enter_postcar(void) void platform_enter_postcar(void)
{ {
struct postcar_frame pcf; struct postcar_frame pcf;
uintptr_t top_of_ram; uintptr_t top_of_ram;
@ -63,8 +64,8 @@ static void platform_enter_postcar(void)
run_postcar_phase(&pcf); run_postcar_phase(&pcf);
} }
/* Entry from cache-as-ram.inc. */ /* Entry from cpu/intel/car/romstage.c. */
static void romstage_main(uint64_t tsc, uint32_t bist) void mainboard_romstage_entry(unsigned long bist)
{ {
struct romstage_params rp = { struct romstage_params rp = {
.bist = bist, .bist = bist,
@ -72,12 +73,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
post_code(0x30); post_code(0x30);
/* Save initial timestamp from bootblock. */
timestamp_init(tsc);
/* Save romstage begin */
timestamp_add_now(TS_START_ROMSTAGE);
/* System Agent Early Initialization */ /* System Agent Early Initialization */
systemagent_early_init(); systemagent_early_init();
@ -131,16 +126,6 @@ static void romstage_main(uint64_t tsc, uint32_t bist)
romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3);
mainboard_post_raminit(&rp); mainboard_post_raminit(&rp);
platform_enter_postcar();
}
/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
* keeping changes in cache_as_ram.S easy to manage.
*/
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
{
romstage_main(base_timestamp, bist);
} }
void __weak mainboard_pre_console_init(void) {} void __weak mainboard_pre_console_init(void) {}