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mb/starlabs/starbook: Adjust TCC Offset for all boards 

Lower the TCC Offset by 10 degress.

Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2023-07-06 12:21:27 +01:00 committed by Matt DeVillier
parent cb40888c8d
commit 5700a1e7f0
2 changed files with 6 additions and 6 deletions
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6
src/mainboard/starlabs/starbook/variants/cml/devtree.c
View File

@ -22,17 +22,17 @@ void devtree_update(void)
disable_turbo(); disable_turbo();
soc_conf->tdp_pl1_override = 15; soc_conf->tdp_pl1_override = 15;
soc_conf->tdp_pl2_override = 15; soc_conf->tdp_pl2_override = 15;
cfg->tcc_offset = 20; cfg->tcc_offset = 30;
break; break;
case PP_BALANCED: case PP_BALANCED:
soc_conf->tdp_pl1_override = 17; soc_conf->tdp_pl1_override = 17;
soc_conf->tdp_pl2_override = 20; soc_conf->tdp_pl2_override = 20;
cfg->tcc_offset = 15; cfg->tcc_offset = 25;
break; break;
case PP_PERFORMANCE: case PP_PERFORMANCE:
soc_conf->tdp_pl1_override = 20; soc_conf->tdp_pl1_override = 20;
soc_conf->tdp_pl2_override = 25; soc_conf->tdp_pl2_override = 25;
cfg->tcc_offset = 10; cfg->tcc_offset = 20;
break; break;
} }

6
src/mainboard/starlabs/starbook/variants/tgl/devtree.c
View File

@ -31,21 +31,21 @@ void devtree_update(void)
soc_conf_4core->tdp_pl1_override = 15; soc_conf_4core->tdp_pl1_override = 15;
soc_conf_2core->tdp_pl2_override = 15; soc_conf_2core->tdp_pl2_override = 15;
soc_conf_4core->tdp_pl2_override = 15; soc_conf_4core->tdp_pl2_override = 15;
cfg->tcc_offset = 20; cfg->tcc_offset = 30;
break; break;
case PP_BALANCED: case PP_BALANCED:
soc_conf_2core->tdp_pl1_override = 15; soc_conf_2core->tdp_pl1_override = 15;
soc_conf_4core->tdp_pl1_override = 15; soc_conf_4core->tdp_pl1_override = 15;
soc_conf_2core->tdp_pl2_override = 25; soc_conf_2core->tdp_pl2_override = 25;
soc_conf_4core->tdp_pl2_override = 25; soc_conf_4core->tdp_pl2_override = 25;
cfg->tcc_offset = 15; cfg->tcc_offset = 25;
break; break;
case PP_PERFORMANCE: case PP_PERFORMANCE:
soc_conf_2core->tdp_pl1_override = 28; soc_conf_2core->tdp_pl1_override = 28;
soc_conf_4core->tdp_pl1_override = 28; soc_conf_4core->tdp_pl1_override = 28;
soc_conf_2core->tdp_pl2_override = 40; soc_conf_2core->tdp_pl2_override = 40;
soc_conf_4core->tdp_pl2_override = 40; soc_conf_4core->tdp_pl2_override = 40;
cfg->tcc_offset = 10; cfg->tcc_offset = 20;
break; break;
} }