soc/amd/common: Add support to read and set SPI speeds from verstage

Currently all SPI speed configurations are done through EFS at build
time. There is a need to apply SPI speed overrides at run-time - eg.
based on board version after assessing the signal integrity. This
override configuration can be carried out by PSP verstage and bootblock.
Export the APIs to set and read SPI speeds from both PSP verstage and
bootblock.

BUG=None
TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I281531e506b56173471b918c746f58d1ad97162c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>

src/soc/amd/common/block/include/amdblocks/psp_efs.h

@@ -7,7 +7,6 @@
 #include <types.h>
 
 #define EFS_OFFSET (0xffffff - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX) + 0x20000 + 1)
-#define EFS_ADDRESS (0xff000000 + EFS_OFFSET)
 
 #define EMBEDDED_FW_SIGNATURE			0x55aa55aa
 

src/soc/amd/common/block/include/amdblocks/spi.h

@@ -116,4 +116,5 @@ void spi_write8(uint8_t reg, uint8_t val);
 void spi_write16(uint8_t reg, uint16_t val);
 void spi_write32(uint8_t reg, uint32_t val);
 
+void fch_spi_config_modes(void);
 #endif /* AMD_BLOCK_SPI_H */

src/soc/amd/common/block/psp/Makefile.inc

@@ -23,5 +23,6 @@ smm-y += psp_gen2.c
 smm-y += psp_smm_gen2.c
 
 bootblock-y += psp_efs.c
+verstage-y += psp_efs.c
 
 endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2

src/soc/amd/common/block/psp/psp_efs.c

@@ -2,13 +2,18 @@
 
 #include <amdblocks/psp_efs.h>
 #include <arch/mmio.h>
+#include <boot_device.h>
+#include <commonlib/region.h>
 #include <types.h>
 
-struct _embedded_firmware *efs = (struct _embedded_firmware *)EFS_ADDRESS;
+static struct _embedded_firmware *efs;
 
 bool efs_is_valid(void)
 {
-	if (efs->signature != EMBEDDED_FW_SIGNATURE)
+	if (!efs)
+		efs = rdev_mmap(boot_device_ro(), EFS_OFFSET, sizeof(*efs));
+
+	if (!efs || efs->signature != EMBEDDED_FW_SIGNATURE)
 		return false;
 
 	return true;

src/soc/amd/common/block/spi/fch_spi.c

@@ -91,7 +91,7 @@ static void fch_spi_set_read_mode(u32 mode)
 	spi_write32(SPI_CNTRL0, val | SPI_READ_MODE(mode));
 }
 
-static void fch_spi_config_modes(void)
+void fch_spi_config_modes(void)
 {
 	uint8_t read_mode, fast_speed;
 	uint8_t normal_speed = CONFIG_NORMAL_READ_SPI_SPEED;

src/soc/amd/common/psp_verstage/fch.c

@@ -161,4 +161,6 @@ void verstage_soc_init(void)
 	printk(BIOS_DEBUG, "Setting up i2c\n");
 	i2c_soc_early_init();
 	printk(BIOS_DEBUG, "i2c setup\n");
+	fch_spi_config_modes();
+	show_spi_speeds_and_modes();
 }