GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

inteltool: update documentation 

- manpage
 - usage message
 - new warning message if -S is used on an unsupported chipset

Change-Id: I1acaa5f4232b65244ec00fd22ec7460d9cc387f1
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/14624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Stefan Tauner 2016-05-05 17:29:39 +02:00 committed by Martin Roth
parent c3ee3f6d7e
commit 572f074971
4 changed files with 25 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
util/inteltool/inteltool.8
View File

@ -1,8 +1,8 @@
.TH INTELTOOL 8 "May 14, 2008"
.TH INTELTOOL 8
.SH NAME
inteltool \- a tool for dumping Intel(R) CPU / chipset configuration parameters
.SH SYNOPSIS
.B inteltool \fR[\fB\-vh?grpmedPMa\fR]
.B inteltool \fR[\fB\-vh?gGrpmedPMaAsfS\fR]
.SH DESCRIPTION
.B inteltool
is a handy little tool for dumping the configuration space of Intel(R)
@ -20,24 +20,33 @@ Show a help text and exit.
Show version information and exit.
.TP
.B "\-a, \-\-all"
Dump all known I/O Controller Hub (ICH) southbridge, Intel(R) northbridge
and Intel(R) Core CPU MSRs.
Dump all known information listed below.
.TP
.B "\-g, \-\-gpio"
Dump I/O Controller Hub (ICH) southbridge GPIO registers.
.TP
.B "\-G, \-\-gpio-diffs"
Show only GPIO register differences from hardware defaults.
.TP
.B "\-r, \-\-rcba"
Dump I/O Controller Hub (ICH) southbridge RCBA registers.
.TP
.B "\-s, \-\-spi"
Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control.
.TP
.B "\-f, \-\-gfx"
Dump graphics registers.
.TP
.B "\-p, \-\-pmbase"
Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
.TP
.B "\-m, \-\-mchbar"
Dump Intel(R) northbridge MCHBAR registers.
.TP
.BR "\-S" " \fIfile\fR, " "\-\-spd=" "\fIfile\fR"
Dump the memory registers as above and store the current timing settings
into \fIfile\fR.
.TP
.B "\-e, \-\-epbar"
Dump Intel(R) northbridge EPBAR registers.
.TP
@ -49,6 +58,9 @@ Dump Intel(R) northbridge PCIEXBAR registers.
.TP
.B "\-M, \-\-msrs"
Dump Intel(R) CPU MSRs.
.TP
.B "\-A, \-\-ambs"
Dump Advanced Memory Buffer (AMB) registers.
.SH BUGS
Please report any bugs on the coreboot mailing list
.RB "(" http://coreboot.org/Mailinglist ")."

6
util/inteltool/inteltool.c
View File

@ -215,7 +215,7 @@ void print_version(void)
void print_usage(const char *name)
{
printf("usage: %s [-vh?gGrpmedPMas]\n", name);
printf("usage: %s [-vh?gGrpmedPMaAsfS]\n", name);
printf("\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
@ -226,7 +226,7 @@ void print_usage(const char *name)
" -r | --rcba: dump southbridge RCBA registers\n"
" -p | --pmbase: dump southbridge Power Management registers\n\n"
" -m | --mchbar: dump northbridge Memory Controller registers\n"
" -S FILE | --spd=FILE: generate spd.bin equivalent to current timings\n"
" -S FILE | --spd=FILE: create a file storing current timings (implies -m)\n"
" -e | --epbar: dump northbridge EPBAR registers\n"
" -d | --dmibar: dump northbridge DMIBAR registers\n"
" -P | --pciexpress: dump northbridge PCIEXBAR registers\n\n"
@ -241,7 +241,7 @@ int main(int argc, char *argv[])
{
struct pci_access *pacc;
struct pci_dev *sb = NULL, *nb, *gfx = NULL, *dev;
const char *dump_spd_file = 0;
const char *dump_spd_file = NULL;
int i, opt, option_index = 0;
unsigned int id;

2
util/inteltool/ivy_memory.c
View File

@ -359,7 +359,7 @@ void ivybridge_dump_timings(const char *dump_spd_file)
printf("/* SPD matching current mode: */\n");
FILE *dump_spd = 0;
FILE *dump_spd = NULL;
if (dump_spd_file) {
dump_spd = fopen (dump_spd_file, "wb");

5
util/inteltool/memory.c
View File

@ -253,6 +253,8 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
printf ("clock_speed_index = %x\n", read_500 (0,0x609, 6) >> 1);
dump_timings ();
if (dump_spd_file != NULL)
printf("\nCreating a memory timings file is not supported on this chipset.\n");
break;
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN_M:
@ -263,6 +265,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN_015c:
ivybridge_dump_timings(dump_spd_file);
break;
default:
if (dump_spd_file != NULL)
printf("\nCreating a memory timings file is not supported on this chipset.\n");
}
unmap_physical((void *)mchbar, size);
return 0;