update Config.lb and add khepri ht chain
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
1bb45d5a42
commit
57398af2a4
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@ -3,36 +3,178 @@ uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses MAINBOARD
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uses ARCH
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#
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#
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uses FALLBACK_SIZE
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uses ROM_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_IMAGE_SIZE
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uses ROM_SECTION_SIZE
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uses ROM_SECTION_OFFSET
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uses CONFIG_ROM_STREAM_START
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uses PAYLOAD_SIZE
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uses _ROMBASE
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uses XIP_ROM_SIZE
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uses XIP_ROM_BASE
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###
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### Set all of the defaults for an x86 architecture
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### Build options
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###
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#
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#
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##
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## Build code for the fallback boot
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##
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option HAVE_FALLBACK_BOOT=1
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##
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## Build code to reset the motherboard from linuxBIOS
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##
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option HAVE_HARD_RESET=1
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##
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## Build code to export a programmable irq routing table
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##
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option HAVE_PIRQ_TABLE=1
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option IRQ_SLOT_COUNT=7
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##
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## Build code to export an x86 MP table
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## Useful for specifying IRQ routing values
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##
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option HAVE_MP_TABLE=1
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##
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## Build code to export a CMOS option table
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##
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option HAVE_OPTION_TABLE=1
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##
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## Build code for SMP support
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## Only worry about 2 micro processors
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##
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option CONFIG_SMP=1
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option CONFIG_MAX_CPUS=2
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##
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## Build code to setup a generic IOAPIC
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##
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option CONFIG_IOAPIC=1
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##
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## Clean up the motherboard id strings
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##
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option MAINBOARD_PART_NUMBER="KHEPRI"
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option MAINBOARD_VENDOR="NEWISYS"
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###
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### Build the objects we have code for in this directory.
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### LinuxBIOS layout values
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###
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##object mainboard.o
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driver mainboard.o
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object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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## ROM_SIZE is the size of boot ROM that this board will use.
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option ROM_SIZE = 524288
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## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
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option ROM_IMAGE_SIZE = 65536
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##
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## Use a small 8K stack
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##
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option STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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option HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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option USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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option ROM_SECTION_SIZE = FALLBACK_SIZE
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option ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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option ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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option ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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option PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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option CONFIG_ROM_STREAM = 1
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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option _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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option XIP_ROM_SIZE=65536
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option XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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#cpu k8 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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##
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## Build the objects we have code for in this directory.
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##
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#object mainboard.o
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driver mainboard.o
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#object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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object reset.o
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./failover.E ./romcc"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./auto.E ./romcc"
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action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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end
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##
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## Build our 16 bit and 32 bit linuxBIOS entry code
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##
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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##
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## Build our reset vector (This is where linuxBIOS is entered)
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##
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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@ -40,109 +182,106 @@ else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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#option MAX_REBOOT_CNT=2
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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#
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###
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### Setup our mtrrs
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###
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##
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## Setup our mtrrs
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##
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mainboardinit cpu/k8/earlymtrr.inc
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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### This is the early phase of linuxBIOS startup
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### Things are delicate and we test to see if we should
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### failover to another image.
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit ./failover.inc
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ldscript /arch/i386/lib/failover.lds
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mainboardinit ./failover.inc
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end
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#
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#
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###
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### Setup the serial port
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### O.k. We aren't just an intermediary anymore!
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#
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#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./romcc ./failover.E"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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end
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##
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## Setup RAM
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##
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/k8/disable_mmx_sse.inc
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#
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8
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end
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southbridge amd/amd8111 "amd8111"
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end
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southbridge amd/amd8131 "amd8131"
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end
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#mainboardinit archi386/smp/secondary.inc
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superio NSC/pc87360
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register "com1" = "{1}"
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register "lpt" = "{1}"
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end
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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#dir /cpu/k8
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cpu k8 "cpu0"
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register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
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config chip.h
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131"
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pci 1:0.0
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pci 1:0.1
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pci 1:1.0
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pci 1:1.1
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end
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southbridge amd/amd8111 "amd8111"
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pci 1:0.0
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pci 1:1.0
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pci 1:1.1
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pci 1:1.2
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pci 1:1.3
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pci 1:1.5
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pci 1:1.6
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superio NSC/pc87360
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pnp 1:2e.0
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pnp 1:2e.1
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pnp 1:2e.2
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pnp 1:2e.3
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pnp 1:2e.4
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pnp 1:2e.5
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pnp 1:2e.6
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pnp 1:2e.7
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pnp 1:2e.8
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pnp 1:2e.9
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pnp 1:2e.a
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register "com1" = "{1, 0, 0x3f8, 4}"
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register "lpt" = "{1}"
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end
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end
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end
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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cpu k8 "cpu0"
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register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
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end
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cpu k8 "cpu1"
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end
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##
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## Include the old serial code for those few places that still need it.
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##
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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