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soc/intel/alderlake: Add support for Raptor Lake S CPUs 

Add PCI IDs, default VR values and power limits for Raptor Lake S
CPUs. Based on docs 639116 and 640555.

TEST=Tested on a MSI PRO Z690-A (ms7d25) with i9-13900K with Ubuntu
22.10 and LinuxBoot (Linux + u-root). Also tested on MSI PRO Z790-P
with i5-13600K (UEFI Payload) usign RPL-S IoT FSP and Ubuntu 22.04.

Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155
Signed-off-by: Max Fritz <antischmock@googlemail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69798
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
This commit is contained in:
Max Fritz 2022-11-19 01:54:44 +01:00 committed by Felix Held
parent 5787bd21c7
commit 573e6ded9f
13 changed files with 300 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/include/cpu/intel/cpu_ids.h
View File

@ -73,6 +73,10 @@
#define CPUID_METEORLAKE_A0_2 0xa06a1
#define CPUID_METEORLAKE_B0 0xa06a2
#define CPUID_METEORLAKE_C0 0xa06a4
#define CPUID_RAPTORLAKE_S_A0 0xb0670
#define CPUID_RAPTORLAKE_S_B0 0xb0671
#define CPUID_RAPTORLAKE_S_C0 0xb06f2
#define CPUID_RAPTORLAKE_S_H0 0xb06f5
#define CPUID_RAPTORLAKE_P_J0 0xb06a2
#define CPUID_RAPTORLAKE_P_Q0 0xb06a3

9
src/include/device/pci_ids.h
View File

@ -4048,6 +4048,10 @@
#define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50
#define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55
#define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60
#define PCI_DID_INTEL_RPL_S_GT0 0xa79f
#define PCI_DID_INTEL_RPL_S_GT1_1 0xa780
#define PCI_DID_INTEL_RPL_S_GT1_2 0xa782
#define PCI_DID_INTEL_RPL_S_GT1_3 0xa783
#define PCI_DID_INTEL_RPL_P_GT1 0xa720
#define PCI_DID_INTEL_RPL_P_GT2 0xa7a8
#define PCI_DID_INTEL_RPL_P_GT3 0xa7a0
@ -4173,6 +4177,11 @@
#define PCI_DID_INTEL_MTL_P_ID_3 0x7d14
#define PCI_DID_INTEL_MTL_P_ID_4 0x7d15
#define PCI_DID_INTEL_MTL_P_ID_5 0x7d16
#define PCI_DID_INTEL_RPL_S_ID_1 0xa700
#define PCI_DID_INTEL_RPL_S_ID_2 0xa701
#define PCI_DID_INTEL_RPL_S_ID_3 0xa703
#define PCI_DID_INTEL_RPL_S_ID_4 0xa704
#define PCI_DID_INTEL_RPL_S_ID_5 0xa705
#define PCI_DID_INTEL_RPL_P_ID_1 0xa706
#define PCI_DID_INTEL_RPL_P_ID_2 0xa707
#define PCI_DID_INTEL_RPL_P_ID_3 0xa708

1
src/soc/intel/alderlake/Makefile.inc
View File

@ -77,6 +77,7 @@ ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y)
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05
# RPL-S/HX B0
cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01
# 06-b7-00, 06-b7-02, 06-b7-05 RPL-S/HX A0, C0 and H0 missing
else
ifneq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
# 06-9a-00, 06-9a-01 are ADL-P/ADL-M Engineering Samples

20
src/soc/intel/alderlake/bootblock/report_platform.c
View File

@ -34,6 +34,10 @@ static struct {
{ CPUID_ALDERLAKE_S_C0, "Alderlake-S C0 Platform" },
{ CPUID_ALDERLAKE_S_G0, "Alderlake-S G0 Platform" },
{ CPUID_ALDERLAKE_S_H0, "Alderlake-S H0 Platform" },
{ CPUID_RAPTORLAKE_S_A0, "Raptorlake-S A0 Platform" },
{ CPUID_RAPTORLAKE_S_B0, "Raptorlake-S B0 Platform" },
{ CPUID_RAPTORLAKE_S_C0, "Raptorlake-S C0 Platform" },
{ CPUID_RAPTORLAKE_S_H0, "Raptorlake-S H0 Platform" },
{ CPUID_RAPTORLAKE_P_J0, "Raptorlake-P J0 Platform" },
{ CPUID_RAPTORLAKE_P_Q0, "Raptorlake-P Q0 Platform" },
};
@ -76,7 +80,11 @@ static struct {
{ PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" },
{ PCI_DID_INTEL_RPL_P_ID_4, "Raptorlake-P" },
{ PCI_DID_INTEL_RPL_P_ID_5, "Raptorlake-P" },
{ PCI_DID_INTEL_RPL_S_ID_1, "Raptorlake-S (8+16)" },
{ PCI_DID_INTEL_RPL_S_ID_2, "Raptorlake-S (8+0)" },
{ PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (8+8)" },
{ PCI_DID_INTEL_RPL_S_ID_4, "Raptorlake-S (6+8)" },
{ PCI_DID_INTEL_RPL_S_ID_5, "Raptorlake-S (6+4)" },
};
static struct {
@ -101,9 +109,9 @@ static struct {
{ PCI_DID_INTEL_RPP_S_ESPI_1, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_2, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_3, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_4, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_5, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_6, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_4, "Raptorlake-S Z790" },
{ PCI_DID_INTEL_RPP_S_ESPI_5, "Raptorlake-S H770" },
{ PCI_DID_INTEL_RPP_S_ESPI_6, "Raptorlake-S B760" },
{ PCI_DID_INTEL_RPP_S_ESPI_7, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_8, "Raptorlake-S SKU" },
{ PCI_DID_INTEL_RPP_S_ESPI_9, "Raptorlake-S SKU" },
@ -205,6 +213,10 @@ static struct {
{ PCI_DID_INTEL_RPL_P_GT4, "Raptorlake P GT4" },
{ PCI_DID_INTEL_RPL_P_GT5, "Raptorlake P GT5" },
{ PCI_DID_INTEL_RPL_P_GT6, "Raptorlake P GT6" },
{ PCI_DID_INTEL_RPL_S_GT0, "Raptorlake S GT0" },
{ PCI_DID_INTEL_RPL_S_GT1_1, "Raptorlake S GT1" },
{ PCI_DID_INTEL_RPL_S_GT1_2, "Raptorlake S GT1" },
{ PCI_DID_INTEL_RPL_S_GT1_3, "Raptorlake S GT1" }
};
static inline uint8_t get_dev_revision(pci_devfn_t dev)

49
src/soc/intel/alderlake/chip.h
View File

@ -72,6 +72,29 @@ enum soc_intel_alderlake_power_limits {
RPL_P_682_642_482_45W_CORE,
RPL_P_682_482_282_28W_CORE,
RPL_P_282_242_142_15W_CORE,
RPL_S_8161_35W_CORE,
RPL_S_8161_65W_CORE,
RPL_S_8161_95W_CORE,
RPL_S_8161_125W_CORE,
RPL_S_8161_150W_CORE,
RPL_S_881_35W_CORE,
RPL_S_881_65W_CORE,
RPL_S_881_125W_CORE,
RPL_S_681_35W_CORE,
RPL_S_681_65W_CORE,
RPL_S_681_125W_CORE,
RPL_S_641_35W_CORE,
RPL_S_641_65W_CORE,
RPL_S_641_125W_CORE,
RPL_S_801_80W_CORE,
RPL_S_801_95W_CORE,
RPL_S_401_35W_CORE,
RPL_S_401_58W_CORE,
RPL_S_401_60W_CORE,
RPL_S_401_65W_CORE,
RPL_S_201_35W_CORE,
RPL_S_201_46W_CORE,
RPL_S_201_65W_CORE,
ADL_POWER_LIMITS_COUNT
};
@ -89,6 +112,9 @@ enum soc_intel_alderlake_cpu_tdps {
TDP_58W = 58,
TDP_60W = 60,
TDP_65W = 65,
TDP_80W = 80,
TDP_90W = 90,
TDP_95W = 95,
TDP_125W = 125,
TDP_150W = 150
};
@ -139,6 +165,29 @@ static const struct {
{ PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W },
{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_125W_CORE, TDP_125W },
{ PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_150W_CORE, TDP_150W },
{ PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_125W_CORE, TDP_125W },
{ PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_125W_CORE, TDP_125W },
{ PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_125W_CORE, TDP_125W },
{ PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_80W_CORE, TDP_80W },
{ PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_95W_CORE, TDP_90W },
{ PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_58W_CORE, TDP_58W },
{ PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_60W_CORE, TDP_60W },
{ PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_65W_CORE, TDP_65W },
{ PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_35W_CORE, TDP_35W },
{ PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_46W_CORE, TDP_46W },
{ PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_65W_CORE, TDP_65W },
};
/* Types of display ports */

138
src/soc/intel/alderlake/chipset_pch_s.cb
View File

@ -92,6 +92,144 @@ chip soc/intel/alderlake
.tdp_pl4 = 44,
}"
register "power_limits_config[RPL_S_8161_35W_CORE]" = "{
.tdp_pl1_override = 35,
.tdp_pl2_override = 106,
.tdp_pl4 = 194,
}"
register "power_limits_config[RPL_S_8161_65W_CORE]" = "{
.tdp_pl1_override = 65,
.tdp_pl2_override = 219,
.tdp_pl4 = 341,
}"
register "power_limits_config[RPL_S_8161_95W_CORE]" = "{
.tdp_pl1_override = 95,
.tdp_pl2_override = 253,
.tdp_pl4 = 380,
}"
register "power_limits_config[RPL_S_8161_125W_CORE]" = "{
.tdp_pl1_override = 125,
.tdp_pl2_override = 253,
.tdp_pl4 = 380,
}"
register "power_limits_config[RPL_S_8161_150W_CORE]" = "{
.tdp_pl1_override = 125,
.tdp_pl2_override = 253,
.tdp_pl4 = 380,
}"
register "power_limits_config[RPL_S_881_35W_CORE]" = "{
.tdp_pl1_override = 35,
.tdp_pl2_override = 106,
.tdp_pl4 = 194,
}"
register "power_limits_config[RPL_S_881_65W_CORE]" = "{
.tdp_pl1_override = 65,
.tdp_pl2_override = 219,
.tdp_pl4 = 341,
}"
register "power_limits_config[RPL_S_881_125W_CORE]" = "{
.tdp_pl1_override = 125,
.tdp_pl2_override = 253,
.tdp_pl4 = 380,
}"
register "power_limits_config[RPL_S_681_35W_CORE]" = "{
.tdp_pl1_override = 35,
.tdp_pl2_override = 92,
.tdp_pl4 = 136,
}"
register "power_limits_config[RPL_S_681_65W_CORE]" = "{
.tdp_pl1_override = 65,
.tdp_pl2_override = 153,
.tdp_pl4 = 212,
}"
register "power_limits_config[RPL_S_681_125W_CORE]" = "{
.tdp_pl1_override = 125,
.tdp_pl2_override = 181,
.tdp_pl4 = 285,
}"
register "power_limits_config[RPL_S_641_35W_CORE]" = "{
.tdp_pl1_override = 35,
.tdp_pl2_override = 82,
.tdp_pl4 = 124,
}"
register "power_limits_config[RPL_S_641_65W_CORE]" = "{
.tdp_pl1_override = 65,
.tdp_pl2_override = 148,
.tdp_pl4 = 194,
}"
register "power_limits_config[RPL_S_641_125W_CORE]" = "{
.tdp_pl1_override = 125,
.tdp_pl2_override = 181,
.tdp_pl4 = 285,
}"
register "power_limits_config[RPL_S_801_80W_CORE]" = "{
.tdp_pl1_override = 80,
.tdp_pl2_override = 253,
.tdp_pl4 = 380,
}"
register "power_limits_config[RPL_S_801_95W_CORE]" = "{
.tdp_pl1_override = 95,
.tdp_pl2_override = 253,
.tdp_pl4 = 380,
}"
register "power_limits_config[RPL_S_401_35W_CORE]" = "{
.tdp_pl1_override = 35,
.tdp_pl2_override = 69,
.tdp_pl4 = 98,
}"
register "power_limits_config[RPL_S_401_58W_CORE]" = "{
.tdp_pl1_override = 58,
.tdp_pl2_override = 89,
.tdp_pl4 = 125,
}"
register "power_limits_config[RPL_S_401_60W_CORE]" = "{
.tdp_pl1_override = 60,
.tdp_pl2_override = 89,
.tdp_pl4 = 125,
}"
register "power_limits_config[RPL_S_401_65W_CORE]" = "{
.tdp_pl1_override = 65,
.tdp_pl2_override = 89,
.tdp_pl4 = 125,
}"
register "power_limits_config[RPL_S_201_35W_CORE]" = "{
.tdp_pl1_override = 35,
.tdp_pl2_override = 35,
.tdp_pl4 = 44,
}"
register "power_limits_config[RPL_S_201_46W_CORE]" = "{
.tdp_pl1_override = 46,
.tdp_pl2_override = 46,
.tdp_pl4 = 57,
}"
register "power_limits_config[RPL_S_201_65W_CORE]" = "{
.tdp_pl1_override = 65,
.tdp_pl2_override = 65,
.tdp_pl4 = 65,
}"
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file.

14
src/soc/intel/alderlake/cpu.c
View File

@ -242,6 +242,14 @@ enum adl_cpu_type get_adl_cpu_type(void)
PCI_DID_INTEL_ADL_N_ID_4,
};
const uint16_t rpl_s_mch_ids[] = {
PCI_DID_INTEL_RPL_S_ID_1,
PCI_DID_INTEL_RPL_S_ID_2,
PCI_DID_INTEL_RPL_S_ID_3,
PCI_DID_INTEL_RPL_S_ID_4,
PCI_DID_INTEL_RPL_S_ID_5
};
const uint16_t rpl_p_mch_ids[] = {
PCI_DID_INTEL_RPL_P_ID_1,
PCI_DID_INTEL_RPL_P_ID_2,
@ -269,6 +277,11 @@ enum adl_cpu_type get_adl_cpu_type(void)
return ADL_S;
}
for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) {
if (rpl_s_mch_ids[i] == mchid)
return RPL_S;
}
for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) {
if (adl_n_mch_ids[i] == mchid)
return ADL_N;
@ -292,6 +305,7 @@ uint8_t get_supported_lpm_mask(void)
case RPL_P:
return LPM_S0i2_0 | LPM_S0i3_0;
case ADL_S:
case RPL_S:
return LPM_S0i2_0 | LPM_S0i2_1;
default:
printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type);

7
src/soc/intel/alderlake/fsp_params.c
View File

@ -50,6 +50,7 @@
#define ICC_MAX_ID_ADL_M_MA 12000
#define ICC_MAX_ID_ADL_N_MA 27000
#define ICC_MAX_ADL_S 33000
#define ICC_MAX_RPL_S 36000
/*
* ME End of Post configuration
@ -539,6 +540,12 @@ static uint16_t get_vccin_aux_imon_iccmax(void)
case PCI_DID_INTEL_ADL_S_ID_11:
case PCI_DID_INTEL_ADL_S_ID_12:
return ICC_MAX_ADL_S;
case PCI_DID_INTEL_RPL_S_ID_1:
case PCI_DID_INTEL_RPL_S_ID_2:
case PCI_DID_INTEL_RPL_S_ID_3:
case PCI_DID_INTEL_RPL_S_ID_4:
case PCI_DID_INTEL_RPL_S_ID_5:
return ICC_MAX_RPL_S;
default:
printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n",
mch_id);

1
src/soc/intel/alderlake/include/soc/cpu.h
View File

@ -26,6 +26,7 @@ enum adl_cpu_type {
ADL_P,
ADL_S,
RPL_P,
RPL_S,
};
enum adl_cpu_type get_adl_cpu_type(void);

48
src/soc/intel/alderlake/vr_config.c
View File

@ -147,6 +147,18 @@ static const struct vr_lookup vr_config_ll[] = {
{ PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
{ PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
{ PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) },
{ PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) },
};
static const struct vr_lookup vr_config_icc[] = {
@ -186,6 +198,18 @@ static const struct vr_lookup vr_config_icc[] = {
{ PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_ICC(90, 30) },
{ PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_ICC(49, 30) },
{ PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_ICC(37, 30) },
{ PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(307, 30) },
{ PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) },
{ PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) },
{ PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) },
{ PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) },
{ PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) },
{ PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) },
{ PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_ICC(200, 30) },
{ PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_ICC(160, 30) },
{ PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_ICC(120, 30) },
{ PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_ICC(140, 30) },
{ PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) },
};
static const struct vr_lookup vr_config_tdc_timewindow[] = {
@ -225,6 +249,18 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = {
{ PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
{ PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) },
};
static const struct vr_lookup vr_config_tdc_currentlimit[] = {
@ -264,6 +300,18 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = {
{ PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 20) },
{ PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 20) },
{ PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 20) },
{ PCI_DID_INTEL_RPL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(153, 22) },
{ PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) },
{ PCI_DID_INTEL_RPL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) },
{ PCI_DID_INTEL_RPL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) },
{ PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) },
{ PCI_DID_INTEL_RPL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) },
{ PCI_DID_INTEL_RPL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) },
{ PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(114, 22) },
{ PCI_DID_INTEL_RPL_S_ID_4, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(78, 22) },
{ PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(51, 22) },
{ PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(69, 22) },
{ PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 22) },
};
static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg,

4
src/soc/intel/common/block/cpu/mp_init.c
View File

@ -83,6 +83,10 @@ static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0, CPUID_EXACT_MATCH_MASK },
{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_J0, CPUID_EXACT_MATCH_MASK },
{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_Q0, CPUID_EXACT_MATCH_MASK },
{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_A0, CPUID_EXACT_MATCH_MASK },
{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_B0, CPUID_EXACT_MATCH_MASK },
{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_C0, CPUID_EXACT_MATCH_MASK },
{ X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_H0, CPUID_EXACT_MATCH_MASK },
CPU_TABLE_END
};

4
src/soc/intel/common/block/graphics/graphics.c
View File

@ -312,6 +312,10 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_ADL_N_GT1,
PCI_DID_INTEL_ADL_N_GT2,
PCI_DID_INTEL_ADL_N_GT3,
PCI_DID_INTEL_RPL_S_GT0,
PCI_DID_INTEL_RPL_S_GT1_1,
PCI_DID_INTEL_RPL_S_GT1_2,
PCI_DID_INTEL_RPL_S_GT1_3,
0,
};

5
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -436,6 +436,11 @@ static const unsigned short systemagent_ids[] = {
PCI_DID_INTEL_ADL_N_ID_2,
PCI_DID_INTEL_ADL_N_ID_3,
PCI_DID_INTEL_ADL_N_ID_4,
PCI_DID_INTEL_RPL_S_ID_1,
PCI_DID_INTEL_RPL_S_ID_2,
PCI_DID_INTEL_RPL_S_ID_3,
PCI_DID_INTEL_RPL_S_ID_4,
PCI_DID_INTEL_RPL_S_ID_5,
PCI_DID_INTEL_RPL_P_ID_1,
PCI_DID_INTEL_RPL_P_ID_2,
PCI_DID_INTEL_RPL_P_ID_3,