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soc/amd/cezanne: add basic romstage 

This currently only initializes the console, calls into the FSP driver
that then calls into FSP-M and then jumps to ramstage after the FSP-M
returns. Right now, this mainly unblocks the FSP-M development.

Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-01-14 01:16:56 +01:00
parent 8d0a609e6d
commit 57419de187
1 changed files with 13 additions and 0 deletions
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13
src/soc/amd/cezanne/romstage.c
View File

@ -1,7 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/api.h>
#include <program_loading.h>
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
@ -9,4 +11,15 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
asmlinkage void car_stage_entry(void)
{
post_code(0x40);
console_init();
post_code(0x41);
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
fsp_memory_init(false); /* no S3 resume yet */
run_ramstage();
}