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mb/{lenovo/x201,packardbell/ms2290}: Remove superfluous TS init 

Timestamps are initialized in cpu/intel/car/romstage.c.

Change-Id: Ia2b762667be17aa5b482cd585dd6f6198cf50d9e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32758
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-05-12 14:11:00 +02:00 committed by Patrick Rudolph
parent 55cb5f8de5
commit 57459dbeac
2 changed files with 0 additions and 8 deletions
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4
src/mainboard/lenovo/x201/romstage.c
View File

@ -175,10 +175,6 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 };
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();

4
src/mainboard/packardbell/ms2290/romstage.c
View File

@ -168,14 +168,10 @@ void mainboard_romstage_entry(unsigned long bist)
int s3resume = 0;
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
timestamp_init(timestamp_get());
/* SERR pin is confused on reset. Clear NMI. */
outb(4, 0x61);
outb(0, 0x61);
timestamp_add_now(TS_START_ROMSTAGE);
if (bist == 0)
enable_lapic();