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soc/intel/skylake: Assign device ops in chipset devicetree 

Some PCI IDs were missing, and at least one (SPT's fast SPI
device in a generic SPI driver) was wrong. Hence, this patch
actually changes behavior depending on the devices actually
present in a machine.

In this patch the Skylake devicetree is written in a single-line
style. Alternative, the device operations could be put on a separate
line, e.g.
    device pci 00.0 alias system_agent on
            ops systemagent_ops
    end

Tested on Kontron/bSL6. Notable in the log diff is that the
CSE and SATA drivers are hooked up now.

Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Nico Huber 2022-08-06 19:11:55 +02:00 committed by Felix Held
parent c0fc38eed8
commit 576861994e
19 changed files with 94 additions and 272 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/intel/common/block/cse/cse.c
View File

@ -1274,7 +1274,7 @@ static void cse_final(struct device *dev)
cse_final_end_of_firmware(); cse_final_end_of_firmware();
} }
static struct device_operations cse_ops = { struct device_operations cse_ops = {
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -1289,7 +1289,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_APL_CSE0, PCI_DID_INTEL_APL_CSE0,
PCI_DID_INTEL_GLK_CSE0, PCI_DID_INTEL_GLK_CSE0,
PCI_DID_INTEL_CNL_CSE0, PCI_DID_INTEL_CNL_CSE0,
PCI_DID_INTEL_SKL_CSE0,
PCI_DID_INTEL_LWB_CSE0, PCI_DID_INTEL_LWB_CSE0,
PCI_DID_INTEL_LWB_CSE0_SUPER, PCI_DID_INTEL_LWB_CSE0_SUPER,
PCI_DID_INTEL_CNP_H_CSE0, PCI_DID_INTEL_CNP_H_CSE0,

2
src/soc/intel/common/block/gpio/gpio_dev.c
View File

@ -15,7 +15,7 @@ static struct gpio_operations gpio_ops = {
.output = gpio_output, .output = gpio_output,
}; };
static struct device_operations block_gpio_ops = { struct device_operations block_gpio_ops = {
.read_resources = noop_read_resources, .read_resources = noop_read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.ops_gpio = &gpio_ops, .ops_gpio = &gpio_ops,

31
src/soc/intel/common/block/graphics/graphics.c
View File

@ -175,7 +175,7 @@ static void graphics_dev_read_resources(struct device *dev)
} }
} }
static const struct device_operations graphics_ops = { const struct device_operations graphics_ops = {
.read_resources = graphics_dev_read_resources, .read_resources = graphics_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -213,36 +213,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_GLK_IGD_EU12, PCI_DID_INTEL_GLK_IGD_EU12,
PCI_DID_INTEL_WHL_GT1_ULT_1, PCI_DID_INTEL_WHL_GT1_ULT_1,
PCI_DID_INTEL_WHL_GT2_ULT_1, PCI_DID_INTEL_WHL_GT2_ULT_1,
PCI_DID_INTEL_KBL_GT1_SULTM,
PCI_DID_INTEL_KBL_GT1_SHALM_1,
PCI_DID_INTEL_KBL_GT1_SHALM_2,
PCI_DID_INTEL_KBL_GT1_SSRVM,
PCI_DID_INTEL_KBL_GT1F_DT2,
PCI_DID_INTEL_KBL_GT2_SULXM,
PCI_DID_INTEL_KBL_GT2_SULTM,
PCI_DID_INTEL_KBL_GT2_SULTMR,
PCI_DID_INTEL_KBL_GT2_SSRVM,
PCI_DID_INTEL_KBL_GT2_SWSTM,
PCI_DID_INTEL_KBL_GT2_SHALM,
PCI_DID_INTEL_KBL_GT2_DT2P2,
PCI_DID_INTEL_KBL_GT2F_SULTM,
PCI_DID_INTEL_KBL_GT3E_SULTM_1,
PCI_DID_INTEL_KBL_GT3E_SULTM_2,
PCI_DID_INTEL_KBL_GT4_SHALM,
PCI_DID_INTEL_AML_GT2_ULX, PCI_DID_INTEL_AML_GT2_ULX,
PCI_DID_INTEL_SKL_GT1F_DT2,
PCI_DID_INTEL_SKL_GT1_SULTM,
PCI_DID_INTEL_SKL_GT2_DT2P1,
PCI_DID_INTEL_SKL_GT2_SULXM,
PCI_DID_INTEL_SKL_GT2_SULTM,
PCI_DID_INTEL_SKL_GT2_SHALM,
PCI_DID_INTEL_SKL_GT2_SWKSM,
PCI_DID_INTEL_SKL_GT3_SULTM,
PCI_DID_INTEL_SKL_GT3E_SULTM_1,
PCI_DID_INTEL_SKL_GT3E_SULTM_2,
PCI_DID_INTEL_SKL_GT3FE_SSRVM,
PCI_DID_INTEL_SKL_GT4_SHALM,
PCI_DID_INTEL_SKL_GT4E_SWSTM,
PCI_DID_INTEL_CFL_H_GT2, PCI_DID_INTEL_CFL_H_GT2,
PCI_DID_INTEL_CFL_H_XEON_GT2, PCI_DID_INTEL_CFL_H_XEON_GT2,
PCI_DID_INTEL_CFL_S_GT1_1, PCI_DID_INTEL_CFL_S_GT1_1,

5
src/soc/intel/common/block/hda/hda.c
View File

@ -11,7 +11,7 @@ static void hda_init(struct device *dev)
azalia_audio_init(dev); azalia_audio_init(dev);
} }
static struct device_operations hda_ops = { struct device_operations hda_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -32,11 +32,8 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_RPP_P_AUDIO, PCI_DID_INTEL_RPP_P_AUDIO,
PCI_DID_INTEL_APL_AUDIO, PCI_DID_INTEL_APL_AUDIO,
PCI_DID_INTEL_GLK_AUDIO, PCI_DID_INTEL_GLK_AUDIO,
PCI_DID_INTEL_SKL_AUDIO,
PCI_DID_INTEL_SKL_H_AUDIO,
PCI_DID_INTEL_LWB_AUDIO, PCI_DID_INTEL_LWB_AUDIO,
PCI_DID_INTEL_LWB_AUDIO_SUPER, PCI_DID_INTEL_LWB_AUDIO_SUPER,
PCI_DID_INTEL_KBL_AUDIO,
PCI_DID_INTEL_CNL_AUDIO, PCI_DID_INTEL_CNL_AUDIO,
PCI_DID_INTEL_CNP_H_AUDIO, PCI_DID_INTEL_CNP_H_AUDIO,
PCI_DID_INTEL_ICL_AUDIO, PCI_DID_INTEL_ICL_AUDIO,

12
src/soc/intel/common/block/i2c/i2c.c
View File

@ -161,7 +161,7 @@ static void dw_i2c_device_init(struct device *dev)
dw_i2c_dev_init(dev); dw_i2c_dev_init(dev);
} }
static struct device_operations i2c_dev_ops = { struct device_operations i2c_dev_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -181,16 +181,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_I2C3, PCI_DID_INTEL_MTL_I2C3,
PCI_DID_INTEL_MTL_I2C4, PCI_DID_INTEL_MTL_I2C4,
PCI_DID_INTEL_MTL_I2C5, PCI_DID_INTEL_MTL_I2C5,
PCI_DID_INTEL_SPT_I2C0,
PCI_DID_INTEL_SPT_I2C1,
PCI_DID_INTEL_SPT_I2C2,
PCI_DID_INTEL_SPT_I2C3,
PCI_DID_INTEL_SPT_I2C4,
PCI_DID_INTEL_SPT_I2C5,
PCI_DID_INTEL_UPT_H_I2C0,
PCI_DID_INTEL_UPT_H_I2C1,
PCI_DID_INTEL_UPT_H_I2C2,
PCI_DID_INTEL_UPT_H_I2C3,
PCI_DID_INTEL_APL_I2C0, PCI_DID_INTEL_APL_I2C0,
PCI_DID_INTEL_APL_I2C1, PCI_DID_INTEL_APL_I2C1,
PCI_DID_INTEL_APL_I2C2, PCI_DID_INTEL_APL_I2C2,

37
src/soc/intel/common/block/lpc/lpc.c
View File

@ -124,7 +124,7 @@ static const char *lpc_acpi_name(const struct device *dev)
} }
#endif #endif
static struct device_operations device_ops = { struct device_operations lpc_ops = {
.read_resources = pch_lpc_read_resources, .read_resources = pch_lpc_read_resources,
.set_resources = pch_lpc_set_resources, .set_resources = pch_lpc_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -210,24 +210,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_RPP_S_ESPI_29, PCI_DID_INTEL_RPP_S_ESPI_29,
PCI_DID_INTEL_RPP_S_ESPI_30, PCI_DID_INTEL_RPP_S_ESPI_30,
PCI_DID_INTEL_RPP_S_ESPI_31, PCI_DID_INTEL_RPP_S_ESPI_31,
PCI_DID_INTEL_SPT_LP_SAMPLE,
PCI_DID_INTEL_SPT_LP_U_BASE,
PCI_DID_INTEL_SPT_LP_U_PREMIUM,
PCI_DID_INTEL_SPT_LP_Y_PREMIUM,
PCI_DID_INTEL_SPT_H_H110,
PCI_DID_INTEL_SPT_H_H170,
PCI_DID_INTEL_SPT_H_Z170,
PCI_DID_INTEL_SPT_H_Q170,
PCI_DID_INTEL_SPT_H_Q150,
PCI_DID_INTEL_SPT_H_B150,
PCI_DID_INTEL_SPT_H_C236,
PCI_DID_INTEL_SPT_H_C232,
PCI_DID_INTEL_SPT_H_QM170,
PCI_DID_INTEL_SPT_H_HM170,
PCI_DID_INTEL_SPT_H_CM236,
PCI_DID_INTEL_SPT_H_HM175,
PCI_DID_INTEL_SPT_H_QM175,
PCI_DID_INTEL_SPT_H_CM238,
PCI_DID_INTEL_LWB_C621, PCI_DID_INTEL_LWB_C621,
PCI_DID_INTEL_LWB_C622, PCI_DID_INTEL_LWB_C622,
PCI_DID_INTEL_LWB_C624, PCI_DID_INTEL_LWB_C624,
@ -248,21 +230,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_LWB_C627A_SUPER, PCI_DID_INTEL_LWB_C627A_SUPER,
PCI_DID_INTEL_LWB_C629A_SUPER, PCI_DID_INTEL_LWB_C629A_SUPER,
PCI_DID_INTEL_EMB_SUPER, PCI_DID_INTEL_EMB_SUPER,
PCI_DID_INTEL_UPT_H_Q270,
PCI_DID_INTEL_UPT_H_H270,
PCI_DID_INTEL_UPT_H_Z270,
PCI_DID_INTEL_UPT_H_Q250,
PCI_DID_INTEL_UPT_H_B250,
PCI_DID_INTEL_UPT_H_Z370,
PCI_DID_INTEL_UPT_H_H310C,
PCI_DID_INTEL_UPT_H_B365,
PCI_DID_INTEL_SPT_LP_Y_PREMIUM_HDCP22,
PCI_DID_INTEL_SPT_LP_U_PREMIUM_HDCP22,
PCI_DID_INTEL_SPT_LP_U_BASE_HDCP22,
PCI_DID_INTEL_UPT_LP_SUPER_SKU,
PCI_DID_INTEL_UPT_LP_U_BASE,
PCI_DID_INTEL_UPT_LP_U_PREMIUM,
PCI_DID_INTEL_UPT_LP_Y_PREMIUM,
PCI_DID_INTEL_APL_LPC, PCI_DID_INTEL_APL_LPC,
PCI_DID_INTEL_GLK_LPC, PCI_DID_INTEL_GLK_LPC,
PCI_DID_INTEL_GLK_ESPI, PCI_DID_INTEL_GLK_ESPI,
@ -416,7 +383,7 @@ static const unsigned short pci_device_ids[] = {
}; };
static const struct pci_driver pch_lpc __pci_driver = { static const struct pci_driver pch_lpc __pci_driver = {
.ops = &device_ops, .ops = &lpc_ops,
.vendor = PCI_VID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

7
src/soc/intel/common/block/p2sb/p2sb.c
View File

@ -131,7 +131,7 @@ static void read_resources(struct device *dev)
mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB); mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB);
} }
static const struct device_operations device_ops = { const struct device_operations p2sb_ops = {
.read_resources = read_resources, .read_resources = read_resources,
.set_resources = noop_set_resources, .set_resources = noop_set_resources,
.ops_pci = &pci_dev_ops_pci, .ops_pci = &pci_dev_ops_pci,
@ -144,9 +144,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_GLK_P2SB, PCI_DID_INTEL_GLK_P2SB,
PCI_DID_INTEL_LWB_P2SB, PCI_DID_INTEL_LWB_P2SB,
PCI_DID_INTEL_LWB_P2SB_SUPER, PCI_DID_INTEL_LWB_P2SB_SUPER,
PCI_DID_INTEL_SKL_LP_P2SB,
PCI_DID_INTEL_SKL_P2SB,
PCI_DID_INTEL_KBL_P2SB,
PCI_DID_INTEL_CNL_P2SB, PCI_DID_INTEL_CNL_P2SB,
PCI_DID_INTEL_CNP_H_P2SB, PCI_DID_INTEL_CNP_H_P2SB,
PCI_DID_INTEL_ICL_P2SB, PCI_DID_INTEL_ICL_P2SB,
@ -163,7 +160,7 @@ static const unsigned short pci_device_ids[] = {
}; };
static const struct pci_driver pmc __pci_driver = { static const struct pci_driver pmc __pci_driver = {
.ops = &device_ops, .ops = &p2sb_ops,
.vendor = PCI_VID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

60
src/soc/intel/common/block/pcie/pcie.c
View File

@ -56,7 +56,7 @@ static struct pci_operations pcie_ops = {
.set_subsystem = pci_dev_set_subsystem, .set_subsystem = pci_dev_set_subsystem,
}; };
static struct device_operations device_ops = { struct device_operations pcie_rp_ops = {
.read_resources = pci_bus_read_resources, .read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources, .enable_resources = pci_bus_enable_resources,
@ -81,38 +81,6 @@ static const unsigned short pcie_device_ids[] = {
PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10,
PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11,
PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12, PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12,
PCI_DID_INTEL_SPT_LP_PCIE_RP1,
PCI_DID_INTEL_SPT_LP_PCIE_RP2,
PCI_DID_INTEL_SPT_LP_PCIE_RP3,
PCI_DID_INTEL_SPT_LP_PCIE_RP4,
PCI_DID_INTEL_SPT_LP_PCIE_RP5,
PCI_DID_INTEL_SPT_LP_PCIE_RP6,
PCI_DID_INTEL_SPT_LP_PCIE_RP7,
PCI_DID_INTEL_SPT_LP_PCIE_RP8,
PCI_DID_INTEL_SPT_LP_PCIE_RP9,
PCI_DID_INTEL_SPT_LP_PCIE_RP10,
PCI_DID_INTEL_SPT_LP_PCIE_RP11,
PCI_DID_INTEL_SPT_LP_PCIE_RP12,
PCI_DID_INTEL_SPT_H_PCIE_RP1,
PCI_DID_INTEL_SPT_H_PCIE_RP2,
PCI_DID_INTEL_SPT_H_PCIE_RP3,
PCI_DID_INTEL_SPT_H_PCIE_RP4,
PCI_DID_INTEL_SPT_H_PCIE_RP5,
PCI_DID_INTEL_SPT_H_PCIE_RP6,
PCI_DID_INTEL_SPT_H_PCIE_RP7,
PCI_DID_INTEL_SPT_H_PCIE_RP8,
PCI_DID_INTEL_SPT_H_PCIE_RP9,
PCI_DID_INTEL_SPT_H_PCIE_RP10,
PCI_DID_INTEL_SPT_H_PCIE_RP11,
PCI_DID_INTEL_SPT_H_PCIE_RP12,
PCI_DID_INTEL_SPT_H_PCIE_RP13,
PCI_DID_INTEL_SPT_H_PCIE_RP14,
PCI_DID_INTEL_SPT_H_PCIE_RP15,
PCI_DID_INTEL_SPT_H_PCIE_RP16,
PCI_DID_INTEL_SPT_H_PCIE_RP17,
PCI_DID_INTEL_SPT_H_PCIE_RP18,
PCI_DID_INTEL_SPT_H_PCIE_RP19,
PCI_DID_INTEL_SPT_H_PCIE_RP20,
PCI_DID_INTEL_LWB_PCIE_RP1, PCI_DID_INTEL_LWB_PCIE_RP1,
PCI_DID_INTEL_LWB_PCIE_RP2, PCI_DID_INTEL_LWB_PCIE_RP2,
PCI_DID_INTEL_LWB_PCIE_RP3, PCI_DID_INTEL_LWB_PCIE_RP3,
@ -153,30 +121,6 @@ static const unsigned short pcie_device_ids[] = {
PCI_DID_INTEL_LWB_PCIE_RP18_SUPER, PCI_DID_INTEL_LWB_PCIE_RP18_SUPER,
PCI_DID_INTEL_LWB_PCIE_RP19_SUPER, PCI_DID_INTEL_LWB_PCIE_RP19_SUPER,
PCI_DID_INTEL_LWB_PCIE_RP20_SUPER, PCI_DID_INTEL_LWB_PCIE_RP20_SUPER,
PCI_DID_INTEL_UPT_H_PCIE_RP1,
PCI_DID_INTEL_UPT_H_PCIE_RP2,
PCI_DID_INTEL_UPT_H_PCIE_RP3,
PCI_DID_INTEL_UPT_H_PCIE_RP4,
PCI_DID_INTEL_UPT_H_PCIE_RP5,
PCI_DID_INTEL_UPT_H_PCIE_RP6,
PCI_DID_INTEL_UPT_H_PCIE_RP7,
PCI_DID_INTEL_UPT_H_PCIE_RP8,
PCI_DID_INTEL_UPT_H_PCIE_RP9,
PCI_DID_INTEL_UPT_H_PCIE_RP10,
PCI_DID_INTEL_UPT_H_PCIE_RP11,
PCI_DID_INTEL_UPT_H_PCIE_RP12,
PCI_DID_INTEL_UPT_H_PCIE_RP13,
PCI_DID_INTEL_UPT_H_PCIE_RP14,
PCI_DID_INTEL_UPT_H_PCIE_RP15,
PCI_DID_INTEL_UPT_H_PCIE_RP16,
PCI_DID_INTEL_UPT_H_PCIE_RP17,
PCI_DID_INTEL_UPT_H_PCIE_RP18,
PCI_DID_INTEL_UPT_H_PCIE_RP19,
PCI_DID_INTEL_UPT_H_PCIE_RP20,
PCI_DID_INTEL_UPT_H_PCIE_RP21,
PCI_DID_INTEL_UPT_H_PCIE_RP22,
PCI_DID_INTEL_UPT_H_PCIE_RP23,
PCI_DID_INTEL_UPT_H_PCIE_RP24,
PCI_DID_INTEL_CNL_LP_PCIE_RP1, PCI_DID_INTEL_CNL_LP_PCIE_RP1,
PCI_DID_INTEL_CNL_LP_PCIE_RP2, PCI_DID_INTEL_CNL_LP_PCIE_RP2,
PCI_DID_INTEL_CNL_LP_PCIE_RP3, PCI_DID_INTEL_CNL_LP_PCIE_RP3,
@ -387,7 +331,7 @@ static const unsigned short pcie_device_ids[] = {
}; };
static const struct pci_driver pch_pcie __pci_driver = { static const struct pci_driver pch_pcie __pci_driver = {
.ops = &device_ops, .ops = &pcie_rp_ops,
.vendor = PCI_VID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pcie_device_ids, .devices = pcie_device_ids,
}; };

7
src/soc/intel/common/block/pmc/pmc.c
View File

@ -97,7 +97,7 @@ static void pmc_final(struct device *dev)
pmc_clear_pmcon_sts(); pmc_clear_pmcon_sts();
} }
static struct device_operations device_ops = { struct device_operations pmc_ops = {
.read_resources = pch_pmc_read_resources, .read_resources = pch_pmc_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -116,11 +116,8 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_IOE_P_PMC, PCI_DID_INTEL_MTL_IOE_P_PMC,
PCI_DID_INTEL_RPP_P_PMC, PCI_DID_INTEL_RPP_P_PMC,
PCI_DID_INTEL_DNV_PMC, PCI_DID_INTEL_DNV_PMC,
PCI_DID_INTEL_SPT_LP_PMC,
PCI_DID_INTEL_SPT_H_PMC,
PCI_DID_INTEL_LWB_PMC, PCI_DID_INTEL_LWB_PMC,
PCI_DID_INTEL_LWB_PMC_SUPER, PCI_DID_INTEL_LWB_PMC_SUPER,
PCI_DID_INTEL_UPT_H_PMC,
PCI_DID_INTEL_APL_PMC, PCI_DID_INTEL_APL_PMC,
PCI_DID_INTEL_GLK_PMC, PCI_DID_INTEL_GLK_PMC,
PCI_DID_INTEL_CNP_H_PMC, PCI_DID_INTEL_CNP_H_PMC,
@ -138,7 +135,7 @@ static const unsigned short pci_device_ids[] = {
}; };
static const struct pci_driver pch_pmc __pci_driver = { static const struct pci_driver pch_pmc __pci_driver = {
.ops = &device_ops, .ops = &pmc_ops,
.vendor = PCI_VID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };

5
src/soc/intel/common/block/sata/sata.c
View File

@ -4,7 +4,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
static struct device_operations sata_ops = { struct device_operations sata_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -16,9 +16,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_SATA, PCI_DID_INTEL_MTL_SATA,
PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_1,
PCI_DID_INTEL_RPP_P_SATA_2, PCI_DID_INTEL_RPP_P_SATA_2,
PCI_DID_INTEL_SPT_U_SATA,
PCI_DID_INTEL_SPT_U_Y_PREMIUM_SATA,
PCI_DID_INTEL_SPT_KBL_SATA,
PCI_DID_INTEL_LWB_SATA_AHCI, PCI_DID_INTEL_LWB_SATA_AHCI,
PCI_DID_INTEL_LWB_SSATA_AHCI, PCI_DID_INTEL_LWB_SSATA_AHCI,
PCI_DID_INTEL_LWB_SATA_RAID, PCI_DID_INTEL_LWB_SATA_RAID,

5
src/soc/intel/common/block/scs/sd.c
View File

@ -38,7 +38,7 @@ static void sd_fill_ssdt(const struct device *dev)
} }
#endif #endif
static struct device_operations dev_ops = { struct device_operations sd_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -52,7 +52,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_APL_SD, PCI_DID_INTEL_APL_SD,
PCI_DID_INTEL_CNL_SD, PCI_DID_INTEL_CNL_SD,
PCI_DID_INTEL_GLK_SD, PCI_DID_INTEL_GLK_SD,
PCI_DID_INTEL_SKL_SD,
PCI_DID_INTEL_CNP_H_SD, PCI_DID_INTEL_CNP_H_SD,
PCI_DID_INTEL_ICL_SD, PCI_DID_INTEL_ICL_SD,
PCI_DID_INTEL_CMP_SD, PCI_DID_INTEL_CMP_SD,
@ -63,7 +62,7 @@ static const unsigned short pci_device_ids[] = {
}; };
static const struct pci_driver pch_sd __pci_driver = { static const struct pci_driver pch_sd __pci_driver = {
.ops = &dev_ops, .ops = &sd_ops,
.vendor = PCI_VID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids .devices = pci_device_ids
}; };

4
src/soc/intel/common/block/smbus/smbus.c
View File

@ -38,7 +38,7 @@ static void finalize_smbus(struct device *dev)
tco_lockdown(); tco_lockdown();
} }
static struct device_operations smbus_ops = { struct device_operations smbus_ops = {
.read_resources = smbus_read_resources, .read_resources = smbus_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -56,8 +56,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_GLK_SMBUS, PCI_DID_INTEL_GLK_SMBUS,
PCI_DID_INTEL_CNL_SMBUS, PCI_DID_INTEL_CNL_SMBUS,
PCI_DID_INTEL_CNP_H_SMBUS, PCI_DID_INTEL_CNP_H_SMBUS,
PCI_DID_INTEL_SPT_LP_SMBUS,
PCI_DID_INTEL_SPT_H_SMBUS,
PCI_DID_INTEL_LWB_SMBUS_SUPER, PCI_DID_INTEL_LWB_SMBUS_SUPER,
PCI_DID_INTEL_LWB_SMBUS, PCI_DID_INTEL_LWB_SMBUS,
PCI_DID_INTEL_ICP_LP_SMBUS, PCI_DID_INTEL_ICP_LP_SMBUS,

5
src/soc/intel/common/block/spi/spi.c
View File

@ -110,7 +110,7 @@ static struct spi_bus_operations spi_bus_ops = {
.dev_to_bus = &spi_dev_to_bus, .dev_to_bus = &spi_dev_to_bus,
}; };
static struct device_operations spi_dev_ops = { struct device_operations spi_dev_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -124,9 +124,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_GSPI0, PCI_DID_INTEL_MTL_GSPI0,
PCI_DID_INTEL_MTL_GSPI1, PCI_DID_INTEL_MTL_GSPI1,
PCI_DID_INTEL_MTL_GSPI2, PCI_DID_INTEL_MTL_GSPI2,
PCI_DID_INTEL_SPT_SPI1,
PCI_DID_INTEL_SPT_SPI2,
PCI_DID_INTEL_SPT_SPI3,
PCI_DID_INTEL_APL_SPI0, PCI_DID_INTEL_APL_SPI0,
PCI_DID_INTEL_APL_SPI1, PCI_DID_INTEL_APL_SPI1,
PCI_DID_INTEL_APL_SPI2, PCI_DID_INTEL_APL_SPI2,

17
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -335,7 +335,7 @@ void ssdt_set_above_4g_pci(const struct device *dev)
printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len); printk(BIOS_DEBUG, "PCI space above 4GB MMIO is at 0x%llx, len = 0x%llx\n", touud, len);
} }
static struct device_operations systemagent_ops = { struct device_operations systemagent_ops = {
.read_resources = systemagent_read_resources, .read_resources = systemagent_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -355,23 +355,8 @@ static const unsigned short systemagent_ids[] = {
PCI_DID_INTEL_APL_NB, PCI_DID_INTEL_APL_NB,
PCI_DID_INTEL_CNL_ID_U, PCI_DID_INTEL_CNL_ID_U,
PCI_DID_INTEL_CNL_ID_Y, PCI_DID_INTEL_CNL_ID_Y,
PCI_DID_INTEL_SKL_ID_U,
PCI_DID_INTEL_SKL_ID_Y,
PCI_DID_INTEL_SKL_ID_ULX,
PCI_DID_INTEL_SKL_ID_H_4,
PCI_DID_INTEL_SKL_ID_H_2,
PCI_DID_INTEL_SKL_ID_S_2,
PCI_DID_INTEL_SKL_ID_S_4,
PCI_DID_INTEL_WHL_ID_W_2, PCI_DID_INTEL_WHL_ID_W_2,
PCI_DID_INTEL_WHL_ID_W_4, PCI_DID_INTEL_WHL_ID_W_4,
PCI_DID_INTEL_KBL_ID_S,
PCI_DID_INTEL_SKL_ID_H_EM,
PCI_DID_INTEL_KBL_ID_U,
PCI_DID_INTEL_KBL_ID_Y,
PCI_DID_INTEL_KBL_ID_H,
PCI_DID_INTEL_KBL_U_R,
PCI_DID_INTEL_KBL_ID_DT,
PCI_DID_INTEL_KBL_ID_DT_2,
PCI_DID_INTEL_CFL_ID_U, PCI_DID_INTEL_CFL_ID_U,
PCI_DID_INTEL_CFL_ID_U_2, PCI_DID_INTEL_CFL_ID_U_2,
PCI_DID_INTEL_CFL_ID_H, PCI_DID_INTEL_CFL_ID_H,

15
src/soc/intel/common/block/uart/uart.c
View File

@ -337,7 +337,7 @@ static const char *uart_acpi_name(const struct device *dev)
} }
} }
static struct device_operations device_ops = { struct device_operations uart_ops = {
.read_resources = uart_read_resources, .read_resources = uart_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = uart_common_enable_resources, .enable_resources = uart_common_enable_resources,
@ -351,15 +351,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_UART0, PCI_DID_INTEL_MTL_UART0,
PCI_DID_INTEL_MTL_UART1, PCI_DID_INTEL_MTL_UART1,
PCI_DID_INTEL_MTL_UART2, PCI_DID_INTEL_MTL_UART2,
PCI_DID_INTEL_SPT_UART0,
PCI_DID_INTEL_SPT_UART1,
PCI_DID_INTEL_SPT_UART2,
PCI_DID_INTEL_SPT_H_UART0,
PCI_DID_INTEL_SPT_H_UART1,
PCI_DID_INTEL_SPT_H_UART2,
PCI_DID_INTEL_UPT_H_UART0,
PCI_DID_INTEL_UPT_H_UART1,
PCI_DID_INTEL_UPT_H_UART2,
PCI_DID_INTEL_APL_UART0, PCI_DID_INTEL_APL_UART0,
PCI_DID_INTEL_APL_UART1, PCI_DID_INTEL_APL_UART1,
PCI_DID_INTEL_APL_UART2, PCI_DID_INTEL_APL_UART2,
@ -418,7 +409,7 @@ static const unsigned short pci_device_ids[] = {
}; };
static const struct pci_driver pch_uart __pci_driver = { static const struct pci_driver pch_uart __pci_driver = {
.ops = &device_ops, .ops = &uart_ops,
.vendor = PCI_VID_INTEL, .vendor = PCI_VID_INTEL,
.devices = pci_device_ids, .devices = pci_device_ids,
}; };
@ -426,7 +417,7 @@ static const struct pci_driver pch_uart __pci_driver = {
static void uart_enable(struct device *dev) static void uart_enable(struct device *dev)
{ {
struct soc_intel_common_block_uart_config *conf = dev->chip_info; struct soc_intel_common_block_uart_config *conf = dev->chip_info;
dev->ops = &device_ops; dev->ops = &uart_ops;
dev->device = conf ? conf->devid : 0; dev->device = conf ? conf->devid : 0;
} }

3
src/soc/intel/common/block/xdci/xdci.c
View File

@ -18,7 +18,7 @@ bool xdci_can_enable(unsigned int xdci_devfn)
return is_devfn_enabled(xdci_devfn); return is_devfn_enabled(xdci_devfn);
} }
static struct device_operations usb_xdci_ops = { struct device_operations usb_xdci_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -31,7 +31,6 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_APL_XDCI, PCI_DID_INTEL_APL_XDCI,
PCI_DID_INTEL_CNL_LP_XDCI, PCI_DID_INTEL_CNL_LP_XDCI,
PCI_DID_INTEL_GLK_XDCI, PCI_DID_INTEL_GLK_XDCI,
PCI_DID_INTEL_SPT_LP_XDCI,
PCI_DID_INTEL_CNP_H_XDCI, PCI_DID_INTEL_CNP_H_XDCI,
PCI_DID_INTEL_ICP_LP_XDCI, PCI_DID_INTEL_ICP_LP_XDCI,
PCI_DID_INTEL_CMP_LP_XDCI, PCI_DID_INTEL_CMP_LP_XDCI,

5
src/soc/intel/common/block/xhci/xhci.c
View File

@ -117,7 +117,7 @@ void usb_xhci_disable_unused(bool (*ext_usb_xhci_en_cb)(unsigned int port_type,
__weak void soc_xhci_init(struct device *dev) { /* no-op */ } __weak void soc_xhci_init(struct device *dev) { /* no-op */ }
static struct device_operations usb_xhci_ops = { struct device_operations usb_xhci_ops = {
.read_resources = pci_dev_read_resources, .read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
@ -134,11 +134,8 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_APL_XHCI, PCI_DID_INTEL_APL_XHCI,
PCI_DID_INTEL_CNL_LP_XHCI, PCI_DID_INTEL_CNL_LP_XHCI,
PCI_DID_INTEL_GLK_XHCI, PCI_DID_INTEL_GLK_XHCI,
PCI_DID_INTEL_SPT_LP_XHCI,
PCI_DID_INTEL_SPT_H_XHCI,
PCI_DID_INTEL_LWB_XHCI, PCI_DID_INTEL_LWB_XHCI,
PCI_DID_INTEL_LWB_XHCI_SUPER, PCI_DID_INTEL_LWB_XHCI_SUPER,
PCI_DID_INTEL_UPT_H_XHCI,
PCI_DID_INTEL_CNP_H_XHCI, PCI_DID_INTEL_CNP_H_XHCI,
PCI_DID_INTEL_ICP_LP_XHCI, PCI_DID_INTEL_ICP_LP_XHCI,
PCI_DID_INTEL_CMP_LP_XHCI, PCI_DID_INTEL_CMP_LP_XHCI,

8
src/soc/intel/skylake/chip.c
View File

@ -186,7 +186,7 @@ void soc_init_pre_device(void *chip_info)
pcie_rp_update_devicetree(pch_lp_rp_groups); pcie_rp_update_devicetree(pch_lp_rp_groups);
} }
static struct device_operations pci_domain_ops = { struct device_operations pci_domain_ops = {
.read_resources = &pci_domain_read_resources, .read_resources = &pci_domain_read_resources,
.set_resources = &pci_domain_set_resources, .set_resources = &pci_domain_set_resources,
.scan_bus = &pci_domain_scan_bus, .scan_bus = &pci_domain_scan_bus,
@ -207,12 +207,8 @@ static struct device_operations cpu_bus_ops = {
static void soc_enable(struct device *dev) static void soc_enable(struct device *dev)
{ {
/* Set the operations if it is a special bus type */ /* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &pci_domain_ops;
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops; dev->ops = &cpu_bus_ops;
else if (dev->path.type == DEVICE_PATH_GPIO)
block_gpio_enable(dev);
} }
struct chip_operations soc_intel_skylake_ops = { struct chip_operations soc_intel_skylake_ops = {

135
src/soc/intel/skylake/chipset.cb
View File

@ -1,71 +1,72 @@
chip soc/intel/skylake chip soc/intel/skylake
device domain 0 on device domain 0 on
device gpio 0 alias pch_gpio on end # GPIO ops pci_domain_ops
device pci 00.0 alias system_agent on end # Host Bridge device gpio 0 alias pch_gpio on ops block_gpio_ops end
device pci 01.0 alias peg0 off end # PEG0 device pci 00.0 alias system_agent on ops systemagent_ops end
device pci 01.1 alias peg1 off end # PEG1 device pci 01.0 alias peg0 off end
device pci 01.2 alias peg2 off end # PEG2 device pci 01.1 alias peg1 off end
device pci 02.0 alias igpu off end # Integrated Graphics Device device pci 01.2 alias peg2 off end
device pci 04.0 alias sa_thermal off end # SA thermal subsystem device pci 02.0 alias igpu off ops graphics_ops end
device pci 05.0 alias imgu off end # Imaging Unit device pci 04.0 alias sa_thermal off end
device pci 07.0 alias chap off end # CHAP device pci 05.0 alias imgu off end # Imaging Unit
device pci 08.0 alias gmm off end # Gaussian Mixture Model device pci 07.0 alias chap off end
device pci 13.0 alias ish off end # SensorHub device pci 08.0 alias gmm off end # Gaussian Mixture Model
device pci 14.0 alias south_xhci off end # USB xHCI device pci 13.0 alias ish off end # SensorHub
device pci 14.1 alias south_xdci off end # USB xDCI (OTG) device pci 14.0 alias south_xhci off ops usb_xhci_ops end
device pci 14.2 alias thermal off end # Thermal Subsystem device pci 14.1 alias south_xdci off ops usb_xdci_ops end
device pci 14.3 alias cio off end # CIO device pci 14.2 alias thermal off end
device pci 15.0 alias i2c0 off end # I2C0 device pci 14.3 alias cio off end
device pci 15.1 alias i2c1 off end # I2C1 device pci 15.0 alias i2c0 off ops i2c_dev_ops end
device pci 15.2 alias i2c2 off end # I2C2 device pci 15.1 alias i2c1 off ops i2c_dev_ops end
device pci 15.3 alias i2c3 off end # I2C3 device pci 15.2 alias i2c2 off ops i2c_dev_ops end
device pci 16.0 alias heci1 off end # Management Engine Interface 1 device pci 15.3 alias i2c3 off ops i2c_dev_ops end
device pci 16.1 alias heci2 off end # Management Engine Interface 2 device pci 16.0 alias heci1 off ops cse_ops end
device pci 16.2 alias csme_ider off end # Management Engine IDE-R device pci 16.1 alias heci2 off end
device pci 16.3 alias csme_ktr off end # Management Engine KT Redirection device pci 16.2 alias csme_ider off end # IDE Redirection
device pci 16.4 alias heci3 off end # Management Engine Interface 3 device pci 16.3 alias csme_ktr off end # KT Redirection
device pci 17.0 alias sata off end # SATA device pci 16.4 alias heci3 off end
device pci 19.0 alias uart2 off end # UART2 device pci 17.0 alias sata off ops sata_ops end
device pci 19.1 alias i2c5 off end # I2C5 device pci 19.0 alias uart2 off ops uart_ops end
device pci 19.2 alias i2c4 off end # I2C4 device pci 19.1 alias i2c5 off ops i2c_dev_ops end
device pci 1b.0 alias pcie_rp17 off end # PCI Express Port 17 device pci 19.2 alias i2c4 off ops i2c_dev_ops end
device pci 1b.1 alias pcie_rp18 off end # PCI Express Port 18 device pci 1b.0 alias pcie_rp17 off ops pcie_rp_ops end
device pci 1b.2 alias pcie_rp19 off end # PCI Express Port 19 device pci 1b.1 alias pcie_rp18 off ops pcie_rp_ops end
device pci 1b.3 alias pcie_rp20 off end # PCI Express Port 20 device pci 1b.2 alias pcie_rp19 off ops pcie_rp_ops end
device pci 1b.4 alias pcie_rp21 off end # PCI Express Port 21 device pci 1b.3 alias pcie_rp20 off ops pcie_rp_ops end
device pci 1b.5 alias pcie_rp22 off end # PCI Express Port 22 device pci 1b.4 alias pcie_rp21 off ops pcie_rp_ops end
device pci 1b.6 alias pcie_rp23 off end # PCI Express Port 23 device pci 1b.5 alias pcie_rp22 off ops pcie_rp_ops end
device pci 1b.7 alias pcie_rp24 off end # PCI Express Port 24 device pci 1b.6 alias pcie_rp23 off ops pcie_rp_ops end
device pci 1c.0 alias pcie_rp1 off end # PCI Express Port 1 device pci 1b.7 alias pcie_rp24 off ops pcie_rp_ops end
device pci 1c.1 alias pcie_rp2 off end # PCI Express Port 2 device pci 1c.0 alias pcie_rp1 off ops pcie_rp_ops end
device pci 1c.2 alias pcie_rp3 off end # PCI Express Port 3 device pci 1c.1 alias pcie_rp2 off ops pcie_rp_ops end
device pci 1c.3 alias pcie_rp4 off end # PCI Express Port 4 device pci 1c.2 alias pcie_rp3 off ops pcie_rp_ops end
device pci 1c.4 alias pcie_rp5 off end # PCI Express Port 5 device pci 1c.3 alias pcie_rp4 off ops pcie_rp_ops end
device pci 1c.5 alias pcie_rp6 off end # PCI Express Port 6 device pci 1c.4 alias pcie_rp5 off ops pcie_rp_ops end
device pci 1c.6 alias pcie_rp7 off end # PCI Express Port 7 device pci 1c.5 alias pcie_rp6 off ops pcie_rp_ops end
device pci 1c.7 alias pcie_rp8 off end # PCI Express Port 8 device pci 1c.6 alias pcie_rp7 off ops pcie_rp_ops end
device pci 1d.0 alias pcie_rp9 off end # PCI Express Port 9 device pci 1c.7 alias pcie_rp8 off ops pcie_rp_ops end
device pci 1d.1 alias pcie_rp10 off end # PCI Express Port 10 device pci 1d.0 alias pcie_rp9 off ops pcie_rp_ops end
device pci 1d.2 alias pcie_rp11 off end # PCI Express Port 11 device pci 1d.1 alias pcie_rp10 off ops pcie_rp_ops end
device pci 1d.3 alias pcie_rp12 off end # PCI Express Port 12 device pci 1d.2 alias pcie_rp11 off ops pcie_rp_ops end
device pci 1d.4 alias pcie_rp13 off end # PCI Express Port 13 device pci 1d.3 alias pcie_rp12 off ops pcie_rp_ops end
device pci 1d.5 alias pcie_rp14 off end # PCI Express Port 14 device pci 1d.4 alias pcie_rp13 off ops pcie_rp_ops end
device pci 1d.6 alias pcie_rp15 off end # PCI Express Port 15 device pci 1d.5 alias pcie_rp14 off ops pcie_rp_ops end
device pci 1d.7 alias pcie_rp16 off end # PCI Express Port 16 device pci 1d.6 alias pcie_rp15 off ops pcie_rp_ops end
device pci 1e.0 alias uart0 off end # UART0 device pci 1d.7 alias pcie_rp16 off ops pcie_rp_ops end
device pci 1e.1 alias uart1 off end # UART1 device pci 1e.0 alias uart0 off ops uart_ops end
device pci 1e.2 alias gspi0 off end # GSPI0 device pci 1e.1 alias uart1 off ops uart_ops end
device pci 1e.3 alias gspi1 off end # GSPI1 device pci 1e.2 alias gspi0 off ops spi_dev_ops end
device pci 1e.4 alias emmc off end # EMMC device pci 1e.3 alias gspi1 off ops spi_dev_ops end
device pci 1e.5 alias sdio off end # SDIO device pci 1e.4 alias emmc off end
device pci 1e.6 alias sdxc off end # SDXC device pci 1e.5 alias sdio off end
device pci 1f.0 alias lpc_espi on end # LPC Interface device pci 1e.6 alias sdxc off ops sd_ops end
device pci 1f.1 alias p2sb on end # P2SB device pci 1f.0 alias lpc_espi on ops lpc_ops end
device pci 1f.2 alias pmc on end # Power Management Controller device pci 1f.1 alias p2sb on ops p2sb_ops end
device pci 1f.3 alias hda off end # Intel HDA device pci 1f.2 alias pmc on ops pmc_ops end
device pci 1f.4 alias smbus off end # SMBus device pci 1f.3 alias hda off ops hda_ops end
device pci 1f.5 alias fast_spi off end # PCH SPI device pci 1f.4 alias smbus off ops smbus_ops end
device pci 1f.6 alias gbe off end # GbE device pci 1f.5 alias fast_spi off end
device pci 1f.7 alias tracehub off end # TraceHub device pci 1f.6 alias gbe off end
device pci 1f.7 alias tracehub off end
end end
end end