soc/intel/apollolake: Hook Up SataPortEnable to devicetree

Hook Up SataPortsEnable to the devicetree. As the default value is 0,
set both [0] and [1] in all mainboards so they aren't affected.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/intel/apollolake_rvp/devicetree.cb

@@ -24,7 +24,10 @@ chip soc/intel/apollolake
 		device pci 0e.0 on end	# - Audio
 		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
-		device pci 12.0 on end	# - SATA
+		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
+		end
 		device pci 13.0 on end	# - PCIe-A 0
 		device pci 13.2 on end	# - Onboard Lan
 		device pci 13.3 on end	# - PCIe-A 3

src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb

@@ -124,7 +124,10 @@ chip soc/intel/apollolake
 		device pci 0f.1 on  end # - Heci2
 		device pci 0f.2 on  end # - Heci3
 		device pci 11.0 off end	# - ISH
-		device pci 12.0 on  end	# - SATA
+		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
+		end
 		device pci 13.0 off end	# - PCIe-A 0 Slot 1
 		device pci 13.1 off end	# - PCIe-A 1
 		device pci 13.2 off end	# - PCIe-A 2 Onboard Lan

src/mainboard/intel/leafhill/devicetree.cb

@@ -24,7 +24,10 @@ chip soc/intel/apollolake
 		device pci 0e.0 on end	# - Audio
 		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
-		device pci 12.0 on end	# - SATA
+		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
+		end
 		device pci 13.0 on end	# - PCIe-A 0
 		device pci 13.2 on end	# - Onboard Lan
 		device pci 13.3 on end	# - PCIe-A 3

src/mainboard/intel/minnow3/devicetree.cb

@@ -24,7 +24,10 @@ chip soc/intel/apollolake
 		device pci 0e.0 on end	# - Audio
 		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
-		device pci 12.0 on end	# - SATA
+		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
+		end
 		device pci 13.0 on end	# - PCIe-A 0
 		device pci 13.2 on end	# - Onboard Lan
 		device pci 13.3 on end	# - PCIe-A 3

src/mainboard/kontron/mal10/variants/mal10/devicetree.cb

@@ -21,7 +21,10 @@ chip soc/intel/apollolake
 		device pci 0e.0 on  end # Audio
 		device pci 0f.0 on  end # TXE
 		device pci 11.0 off end # ISH
-		device pci 12.0 on  end # SATA
+		device pci 12.0 on	# SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
+		end
 		device pci 13.0 on      # PCIe-A 1 (Root Port 2)
 			register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"
 		end

src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb

@@ -73,6 +73,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0 - MACPHY

src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb

@@ -71,6 +71,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0

src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb

@@ -68,6 +68,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0

src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb

@@ -52,6 +52,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0

src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb

@@ -71,6 +71,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0

src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb

@@ -42,6 +42,8 @@ chip soc/intel/apollolake
 		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
 			register "DisableSataSalpSupport" = "1"
 		end
 		device pci 13.0 on	# - RP 2 - PCIe A 0

src/mainboard/starlabs/lite/variants/glk/devicetree.cb

@@ -78,7 +78,10 @@ chip soc/intel/apollolake
 		device pci 0f.1 on  end						# Heci2
 		device pci 0f.2 on  end						# Heci3
 		device pci 11.0 off end						# ISH
-		device pci 12.0 on  end						# SATA
+		device pci 12.0 on						# SATA
+			register "SataPortsEnable[0]"	= "1"
+			register "SataPortsEnable[1]"	= "1"
+		end
 		device pci 13.0 off end						# PCIe-A 0 Slot 1
 		device pci 13.1 off end						# PCIe-A 1
 		device pci 13.2 off end						# PCIe-A 2 Onboard Lan

src/mainboard/starlabs/lite/variants/glkr/devicetree.cb

@@ -78,7 +78,10 @@ chip soc/intel/apollolake
 		device pci 0f.1 on  end						# Heci2
 		device pci 0f.2 on  end						# Heci3
 		device pci 11.0 off end						# ISH
-		device pci 12.0 on  end						# SATA
+		device pci 12.0 on						# SATA
+			register "SataPortsEnable[0]"	= "1"
+			register "SataPortsEnable[1]"	= "1"
+		end
 		device pci 13.0 off end						# PCIe-A 0 Slot 1
 		device pci 13.1 off end						# PCIe-A 1
 		device pci 13.2 off end						# PCIe-A 2 Onboard Lan

src/mainboard/up/squared/devicetree.cb

@@ -37,7 +37,10 @@ chip soc/intel/apollolake
 		device pci 0e.0 on end	# - Audio
 		device pci 0f.0 on end	# - TXE
 		device pci 11.0 off end	# - ISH
-		device pci 12.0 on end	# - SATA
+		device pci 12.0 on	# - SATA
+			register "SataPortsEnable[0]" = "1"
+			register "SataPortsEnable[1]" = "1"
+		end
 		device pci 13.0 on end	# - PCIe-A 1 - PcieRootPort[2]
 		device pci 13.1 on end  # - PCIe-A 2 - PcieRootPort[3]
 		device pci 13.2 on end	# - PCIe-A 3 - PcieRootPort[4]

src/soc/intel/apollolake/chip.c

@@ -728,8 +728,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 	silconfig->PavpEnable = CONFIG(PAVP);
 
 	/* SATA config */
-	if (is_devfn_enabled(PCH_DEVFN_SATA))
+	if (is_devfn_enabled(PCH_DEVFN_SATA)) {
 		silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport);
+		memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable,
+			sizeof(silconfig->SataPortsEnable));
+	}
 
 	/* 8254 Timer */
 	bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));

src/soc/intel/apollolake/chip.h

@@ -99,6 +99,9 @@ struct soc_intel_apollolake_config {
 	/* Sata Ports Hot Plug */
 	uint8_t SataPortsHotPlug[2];
 
+	/* Sata Ports Enable */
+	uint8_t SataPortsEnable[2];
+
 	/* Specifies on which IRQ the SCI will internally appear. */
 	uint8_t sci_irq;