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soc/intel/apollolake: Add support for LPDDR4 nWR setting 

nWR (Write-Recovery for AutoPre-charge commands), the programmed value of nWR
is the number of clock cycles the LPDDR4-SDRAM device uses to determine the
starting point of an internal Pre-charge operation after a Write burst with
AP (auto-pre-charge) enabled. For >2133MHz speed parts the nWR needs to
be set to 24 clock cycles. The nWR field, though, is only in the GLK
FSP, so just update that field conditionally based on the GLK Kconfig
option.

BUG=b:112062440
TEST= build test

Change-Id: I1147538f72f4e2f14e32f3657c05f1f505a56fbf
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Ravi Sarawadi 2018-08-03 15:41:31 -07:00 committed by Aaron Durbin
parent 3f16a0f113
commit 577e41c06e
2 changed files with 15 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/apollolake/include/soc/meminit.h
View File

@ -81,6 +81,7 @@ enum {
enum { enum {
ODT_A_B_HIGH_LOW = 0 << 1, ODT_A_B_HIGH_LOW = 0 << 1,
ODT_A_B_HIGH_HIGH = 1 << 1, ODT_A_B_HIGH_HIGH = 1 << 1,
nWR_24 = 1 << 5,
}; };
/* Provide bit swizzling per DQS and byte swapping within a channel. */ /* Provide bit swizzling per DQS and byte swapping within a channel. */

20
src/soc/intel/apollolake/meminit.c
View File

@ -69,8 +69,10 @@ size_t iohole_in_mib(void)
return 2 * (GiB / MiB); return 2 * (GiB / MiB);
} }
static void set_lpddr4_defaults(FSP_M_CONFIG *cfg) static void set_lpddr4_defaults(FSP_M_CONFIG *cfg, int speed)
{ {
uint8_t odt_config;
/* Enable memory down BGA since it's the only LPDDR4 packaging. */ /* Enable memory down BGA since it's the only LPDDR4 packaging. */
cfg->Package = 1; cfg->Package = 1;
cfg->MemoryDown = 1; cfg->MemoryDown = 1;
@ -122,10 +124,16 @@ static void set_lpddr4_defaults(FSP_M_CONFIG *cfg)
/* Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled /* Set CA ODT with default setting of ODT pins of LPDDR4 modules pulled
up to 1.1V. */ up to 1.1V. */
cfg->Ch0_OdtConfig = ODT_A_B_HIGH_HIGH; odt_config = ODT_A_B_HIGH_HIGH;
cfg->Ch1_OdtConfig = ODT_A_B_HIGH_HIGH;
cfg->Ch2_OdtConfig = ODT_A_B_HIGH_HIGH; /* Need to set correct Write-Recovery configuration based on speed. */
cfg->Ch3_OdtConfig = ODT_A_B_HIGH_HIGH; if (IS_ENABLED(CONFIG_SOC_INTEL_GLK) && speed >= LP4_SPEED_2133)
odt_config |= nWR_24;
cfg->Ch0_OdtConfig = odt_config;
cfg->Ch1_OdtConfig = odt_config;
cfg->Ch2_OdtConfig = odt_config;
cfg->Ch3_OdtConfig = odt_config;
} }
struct speed_mapping { struct speed_mapping {
@ -205,7 +213,7 @@ void meminit_lpddr4(FSP_M_CONFIG *cfg, int speed)
printk(BIOS_INFO, "LP4DDR speed is %dMHz\n", speed); printk(BIOS_INFO, "LP4DDR speed is %dMHz\n", speed);
cfg->Profile = fsp_memory_profile(speed); cfg->Profile = fsp_memory_profile(speed);
set_lpddr4_defaults(cfg); set_lpddr4_defaults(cfg, speed);
} }
static void enable_logical_chan0(FSP_M_CONFIG *cfg, static void enable_logical_chan0(FSP_M_CONFIG *cfg,