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Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-29 

Creator:  Hamish Guthrie <hamish@prodigi.ch>

Added NSC pc97317 super-io and added fill character option to config/Options.lb to speed up flash programming


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
arch import user (historical) 2005-07-06 17:11:02 +00:00
parent fcb591ac68
commit 577f185d38
13 changed files with 376 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/config/Options.lb
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@ -92,7 +92,7 @@ define CPU_OPT
comment "Additional per-cpu CFLAGS"
end
define OBJCOPY
default "$(CROSS_COMPILE)objcopy"
default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
export always
comment "Objcopy command"
end

2
src/cpu/amd/model_gx1/cpu_setup.inc
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@ -8,7 +8,7 @@
/* USES: esi, ecx, eax */
#include "gx1def.h"
#include <cpu/amd/gx1def.h>
movl %eax, %ebp /* preserve bist */

2
src/cpu/amd/model_gx1/gx_setup.inc
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@ -6,7 +6,7 @@
Setup the GX_BASE registers on a National Semiconductor Geode CPU
*/
#include "gx1def.h"
#include <cpu/amd/gx1def.h>
movl %eax, %ebp /* Preserve bist */

101
src/cpu/amd/model_gx1/model_gx1_init.c Normal file
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@ -0,0 +1,101 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
#if 0
#include <cpu/amd/gx1def.h>
#include <arch/io.h>
static void gx1_cpu_setup(void)
{
unsigned char rreg;
unsigned char cpu_table[] = {
0xc1, 0x00, /* NO SMIs */
0xc3, 0x14, /* Enable CPU config register */
0x20, 0x00, /* */
0xb8, GX_BASE>>30, /* Enable GXBASE address */
0xc2, 0x00,
0xe8, 0x98,
0xc3, 0xf8, /* Enable CPU config register */
0x00, 0x00
};
unsigned char *cPtr = cpu_table;
while(rreg = *cPtr++) {
unsigned char rval = *cPtr++;
outb(rreg, 0x22);
outb(rval, 0x23);
}
outb(0xff, 0x22); /* DIR1 -- Identification register 1 */
if(inb(0x23) > 0x63) { /* Rev greater than R3 */
outb(0xe8, 0x22);
outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */
outb(0xf0, 0x22);
outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */
outb(0x20, 0x22);
outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */
/* Bit 2 Incrementor margin 10 */
}
}
static void gx1_gx_setup(void)
{
unsigned long gx_setup_table[] = {
GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC,
GX_BASE + DC_GENERAL_CFG, 0,
GX_BASE + DC_UNLOCK, 0,
GX_BASE + BC_DRAM_TOP, 0x3fffffff,
GX_BASE + BC_XMAP_1, 0x60,
GX_BASE + BC_XMAP_2, 0,
GX_BASE + BC_XMAP_3, 0,
GX_BASE + MC_BANK_CFG, 0x00700070,
GX_BASE + MC_MEM_CNTRL1, XBUSARB,
GX_BASE + MC_GBASE_ADD, 0xff,
0, 0
};
unsigned long *gxPtr = gx_setup_table;
unsigned long *gxdPtr;
unsigned long addr;
while(addr = *gxPtr++) {
gxdPtr = (unsigned long *)addr;
*gxdPtr = *gxPtr++;
}
}
#endif
static void model_gx1_init(device_t dev)
{
#if 0
gx1_cpu_setup();
gx1_gx_setup();
#endif
/* Turn on caching if we haven't already */
x86_enable_cache();
/* Enable the local cpu apics */
setup_lapic();
};
static struct device_operations cpu_dev_ops = {
.init = model_gx1_init,
};
static struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_CYRIX, 0x0540 },
{ 0, 0 },
};
static struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

54
src/include/cpu/amd/gx1def.h Normal file
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@ -0,0 +1,54 @@
/*
freebios/src/northbridge/nsc/gx1/gx1def.inc
Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
Defines for the GX1 processor
*/
#define GX_BASE 0x040000000
/**********************************************************************/
/* Display Controller Registers, offset from GX_BASE */
#define DC_UNLOCK 0x8300
#define DC_UNLOCK_MAGIC 0x4758
#define DC_GENERAL_CFG 0x8304
/**********************************************************************/
/* Bus Controller Registers, offset from GX_BASE */
#define BC_DRAM_TOP 0x8000
#define BC_XMAP_1 0x8004
#define BC_XMAP_2 0x8008
#define BC_XMAP_3 0x800c
/**********************************************************************/
/* Memory Controller Registers, offset from GX_BASE */
#define MC_MEM_CNTRL1 0x8400
#define SDCLKSTRT (1<<17)
#define RFSHRATE (0x1ff<<8)
#define RFSHSTAG (0x3<<6)
#define X2CLKADDR (1<<5)
#define RFSHTST (1<<4)
#define XBUSARB (1<<3)
#define SMM_MAP (1<<2)
#define PROGRAM_SDRAM (1<<0)
#define MC_MEM_CNTRL2 0x8404
#define SDCLK_MASK 0x000003c0
#define SDCLKOUT_MASK 0x00000400
#define MC_BANK_CFG 0x8408
#define DIMM_PG_SZ 0x00000070
#define DIMM_SZ 0x00000700
#define DIMM_COMP_BNK 0x00001000
#define DIMM_MOD_BNK 0x00004000
#define MC_SYNC_TIM1 0x840c
#define MC_GBASE_ADD 0x8414

54
src/mainboard/eaglelion/5bcm/Config.lb
View File

@ -126,12 +126,56 @@ dir /pc80
config chip.h
chip northbridge/amd/gx1
device pci_domain 0 on
device pci 0.0 on end
end
device pci_domain 0 on
device pci 0.0 on end
chip southbridge/amd/cs5530
device pci 12.0 on
chip superio/NSC/pc97317
device pnp 2e.0 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
end
device pnp 2e.1 on # Mouse
irq 0x70 = 12
end
device pnp 2e.2 on # RTC
io 0x60 = 0x70
irq 0x70 = 8
end
device pnp 2e.3 off # FDC
end
device pnp 2e.4 on # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.5 on # COM2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.6 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.7 on # GPIO
io 0x60 = 0xe0
end
device pnp 2e.8 on # Power Management
io 0x60 = 0xe800
end
register "com1" = "{115200}"
register "com2" = "{38400}"
end
device pci 12.1 off end # SMI
device pci 12.2 on end # IDE
device pci 12.3 off end # Audio
device pci 12.4 off end # VGA
end
end
end
chip cpu/amd/model_gx1
end
chip cpu/amd/model_gx1
end
end

4
src/mainboard/eaglelion/5bcm/Options.lb
View File

@ -115,9 +115,9 @@ default HOSTCC="gcc"
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
#default TTYS0_BAUD=115200
default TTYS0_BAUD=115200
#default TTYS0_BAUD=57600
default TTYS0_BAUD=38400
#default TTYS0_BAUD=38400
#default TTYS0_BAUD=19200
#default TTYS0_BAUD=9600
#default TTYS0_BAUD=4800

12
src/northbridge/amd/gx1/raminit.c
View File

@ -46,12 +46,12 @@ void do_refresh(void)
{
unsigned int tval, i;
post_code(0x71);
outb(0x71, 0x80);
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
tval |= RFSHTST;
for(i=0; i>NUM_REFRESH; i++)
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
post_code(0x72);
outb(0x72, 0x80);
}
@ -59,7 +59,7 @@ void enable_dimm(void)
{
unsigned int tval, i;
post_code(0x73);
outb(0x73, 0x80);
/* start SDCLCK's */
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
@ -101,7 +101,7 @@ unsigned int tval, i;
for(i=0; i<2000; i++)
outb(0, 0xed);
post_code(0x74);
outb(0x74, 0x80);
}
static unsigned int size_dimm(int dimm_shift)
@ -321,7 +321,7 @@ static void sdram_init(void)
unsigned int mem_config = 0x00700070;
print_debug("Setting up default parameters for memory\r\n");
post_code(0x70);
outb(0x70, 0x80);
setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
@ -350,5 +350,5 @@ unsigned int mem_config = 0x00700070;
setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config);
enable_dimm();
post_code(0x7e);
outb(0x7e, 0x80);
}

2
src/superio/NSC/pc97317/Config.lb Normal file
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@ -0,0 +1,2 @@
config chip.h
object superio.c

26
src/superio/NSC/pc97317/chip.h Normal file
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@ -0,0 +1,26 @@
#ifndef _SUPERIO_NSC_PC97317
#define _SUPERIO_NSC_PC97317
#ifndef PNP_INDEX_REG
#define PNP_INDEX_REG 0x15C
#endif
#ifndef PNP_DATA_REG
#define PNP_DATA_REG 0x15D
#endif
#ifndef SIO_COM1
#define SIO_COM1_BASE 0x3F8
#endif
#ifndef SIO_COM2
#define SIO_COM2_BASE 0x2F8
#endif
extern struct chip_operations superio_NSC_pc97317_ops;
#include <pc80/keyboard.h>
#include <uart8250.h>
struct superio_NSC_pc97317_config {
struct uart8250 com1, com2;
struct pc_keyboard keyboard;
};
#endif /* _SUPERIO_NSC_PC97317 */

10
src/superio/NSC/pc97317/pc97317.h Normal file
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@ -0,0 +1,10 @@
#define PC97317_KBCK 0x00 /* Keyboard */
#define PC97317_KBCM 0x01 /* Mouse */
#define PC97317_RTC 0x02 /* Real-Time Clock */
#define PC97317_FDC 0x03 /* Floppy */
#define PC97317_PP 0x04 /* Parallel port */
#define PC97317_SP2 0x05 /* Com2 */
#define PC97317_SP1 0x06 /* Com1 */
#define PC97317_GPIO 0x07
#define PC97317_PM 0x08 /* Power Management */

33
src/superio/NSC/pc97317/pc97317_early_serial.c Normal file
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@ -0,0 +1,33 @@
#include <arch/romcc_io.h>
#include "pc97317.h"
#define PM_DEV PNP_DEV(0x2e, PC97317_PM)
#define PM_BASE 0xe8
/* The pc97317 needs clocks to be set up before the serial port will operate */
static void pc97317_enable_serial(device_t dev, unsigned iobase)
{
/* Set base address of power management unit */
pnp_set_logical_device(PM_DEV);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE);
pnp_set_enable(dev, 1);
/* Use on-chip clock multiplier */
outb(0x03, PM_BASE);
outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1);
/* Wait for the clock to stabilise */
while(!inb(PM_BASE + 1 & 0x80))
;
/* Set the base address of the port */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
}

90
src/superio/NSC/pc97317/superio.c Normal file
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@ -0,0 +1,90 @@
/* Copyright 2000 AG Electronics Ltd. */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
#include "chip.h"
#include "pc97317.h"
static void init(device_t dev)
{
struct superio_NSC_pc97317_config *conf;
struct resource *res0, *res1;
if (!dev->enabled) {
return;
}
conf = dev->chip_info;
switch(dev->path.u.pnp.device) {
case PC97317_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
case PC97317_SP2:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com2);
break;
case PC97317_KBCK:
/* Enable keyboard */
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0); /* Disable keyboard */
pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */
pnp_set_enable(dev, 1); /* Enable keyboard */
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
break;
#if 0
case PC97317_FDC:
{
unsigned reg;
/* Set up floppy in PS/2 mode */
outb(0x09, SIO_CONFIG_RA);
reg = inb(SIO_CONFIG_RD);
reg = (reg & 0x3F) | 0x40;
outb(reg, SIO_CONFIG_RD);
outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */
break;
}
#endif
default:
break;
}
}
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = pnp_set_resources,
.enable_resources = pnp_enable_resources,
.enable = pnp_enable,
.init = init,
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, },
{ &ops, PC97317_KBCM, PNP_IRQ0 },
{ &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, },
{ &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, },
{ &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, },
{ &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, },
{ &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, },
{ &ops, PC97317_GPIO, PNP_IO0, { 0xfff8, 0 } },
{ &ops, PC97317_PM, PNP_IO0, { 0xfffe, 0 } },
};
static void enable_dev(struct device *dev)
{
pnp_enable_devices(dev, &ops,
sizeof(pnp_dev_info)/sizeof(pnp_dev_info[0]), pnp_dev_info);
}
struct chip_operations superio_NSC_pc97317_ops = {
CHIP_NAME("NSC 97317")
.enable_dev = enable_dev,
};