Revert "vboot2: add verstage"
This reverts commit 320647abda
, because it
introduced the following regression.
$ LANG=C make V=1
Warning: no suitable GCC for arm.
Warning: no suitable GCC for aarch64.
Warning: no suitable GCC for riscv.
/bin/sh: --: invalid option
Usage: /bin/sh [GNU long option] [option] ...
/bin/sh [GNU long option] [option] script-file ...
GNU long options:
--debug
--debugger
--dump-po-strings
--dump-strings
--help
--init-file
--login
--noediting
--noprofile
--norc
--posix
--rcfile
--restricted
--verbose
--version
Shell options:
-ilrsD or -c command or -O shopt_option (invocation only)
-abefhkmnptuvxBCHP or -o option
make: -print-libgcc-file-name: Command not found
It also introduced trailing whitespace.
Change-Id: I50ec00a38e24c854fa926357cd24f9286bf4f66f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8223
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
parent
3bde659445
commit
5780d6f387
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@ -75,7 +75,7 @@ subdirs-y += site-local
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#######################################################################
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# Add source classes and their build options
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classes-y := ramstage romstage bootblock smm smmstub cpu_microcode verstage
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classes-y := ramstage romstage bootblock smm smmstub cpu_microcode
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# Add dynamic classes for rmodules
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$(foreach supported_arch,$(ARCH_SUPPORTED), \
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@ -128,8 +128,6 @@ ramstage-postprocess=$(foreach d,$(sort $(dir $(1))), \
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$(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(1)); $$(LD_ramstage) -o $$@ -r $$^ ) \
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$(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(call files-in-dir,$(d),$(1)),$(ramstage-objs))))
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verstage-c-ccopts:=-D__PRE_RAM__ -D__VER_STAGE__
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verstage-S-ccopts:=-D__PRE_RAM__ -D__VER_STAGE__
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romstage-c-ccopts:=-D__PRE_RAM__
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romstage-S-ccopts:=-D__PRE_RAM__
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ifeq ($(CONFIG_TRACE),y)
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@ -164,7 +162,6 @@ endif
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ramstage-c-deps:=$$(OPTION_TABLE_H)
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romstage-c-deps:=$$(OPTION_TABLE_H)
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verstage-c-deps:=$$(OPTION_TABLE_H)
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bootblock-c-deps:=$$(OPTION_TABLE_H)
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smm-c-deps:=$$(OPTION_TABLE_H)
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@ -377,10 +374,6 @@ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(CC_romstage) -MMD $(CFLAGS_romstage) $(CPPFLAGS_romstage) $(romstage-c-ccopts) -c -o $@ $<
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$(obj)/%.verstage.o $(abspath $(obj))/%.verstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(CC_verstage) -MMD $(CFLAGS_verstage) $(verstage-c-ccopts) -c -o $@ $<
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$(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
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@printf " CC $(subst $(obj)/,,$(@))\n"
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$(CC_bootblock) -MMD $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) $(bootblock-c-ccopts) -c -o $@ $<
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@ -3,10 +3,6 @@ config ARCH_BOOTBLOCK_ARM
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default n
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select ARCH_ARM
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config ARCH_VERSTAGE_ARM
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bool
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default n
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config ARCH_ROMSTAGE_ARM
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bool
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default n
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@ -61,7 +61,7 @@ bootblock-y += memcpy.S
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bootblock-y += memmove.S
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bootblock-y += div0.c
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$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $$(VERSTAGE_LIB)
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$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) --start-group $(bootblock-objs) --end-group -T $(src)/arch/arm/bootblock.ld
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@ -2,10 +2,6 @@ config ARCH_BOOTBLOCK_ARMV7
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def_bool n
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select ARCH_BOOTBLOCK_ARM
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config ARCH_VERSTAGE_ARMV7
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def_bool n
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select ARCH_VERSTAGE_ARM
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config ARCH_ROMSTAGE_ARMV7
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def_bool n
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select ARCH_ROMSTAGE_ARM
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@ -2,7 +2,6 @@ config SOC_NVIDIA_TEGRA124
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bool
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default n
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select ARCH_BOOTBLOCK_ARMV4
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select ARCH_VERSTAGE_ARMV7
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select ARCH_ROMSTAGE_ARMV7
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select ARCH_RAMSTAGE_ARMV7
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select HAVE_UART_SPECIAL
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@ -20,8 +20,6 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
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bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c
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endif
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verstage-y += verstage.c
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romstage-y += cbfs.c
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romstage-y += cbmem.c
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romstage-y += clock.c
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@ -23,13 +23,10 @@
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#include <console/console.h>
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#include <soc/clock.h>
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#include <soc/nvidia/tegra/apbmisc.h>
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#include "pinmux.h"
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#include "power.h"
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#if CONFIG_VBOOT2_VERIFY_FIRMWARE
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#include "verstage.h"
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#endif
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void main(void)
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{
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void *entry;
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@ -75,11 +72,7 @@ void main(void)
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power_enable_cpu_rail();
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power_ungate_cpu();
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#if CONFIG_VBOOT2_VERIFY_FIRMWARE
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entry = (void *)verstage_vboot_main;
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#else
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entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
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#endif
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if (entry)
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clock_cpu0_config_and_reset(entry);
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@ -1,9 +0,0 @@
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#include "verstage.h"
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/**
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* Stage entry point
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*/
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void vboot_main(void)
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{
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for(;;);
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}
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@ -1,2 +0,0 @@
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void vboot_main(void);
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void verstage_vboot_main(void);
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@ -85,14 +85,6 @@ config VBOOT_VERIFY_FIRMWARE
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Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the ramstage
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and boot loader.
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config VBOOT2_VERIFY_FIRMWARE
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bool "Firmware Verification with vboot2"
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default n
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depends on CHROMEOS
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help
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Enabling VBOOT2_VERIFY_FIRMWARE will use vboot2 to verify the romstage
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and boot loader.
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config EC_SOFTWARE_SYNC
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bool "Enable EC software sync"
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default n
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@ -93,12 +93,3 @@ $(VB_LIB):
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fwlib
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endif
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ifeq ($(CONFIG_VBOOT2_VERIFY_FIRMWARE),y)
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VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a
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$(VERSTAGE_LIB): $$(verstage-objs)
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@printf " AR $(subst $(obj)/,,$(@))\n"
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$(AR_verstage) rc $@.tmp $(verstage-objs)
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@printf " OBJCOPY $(subst $(obj)/,,$(@))\n"
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$(OBJCOPY_verstage) --prefix-symbols=verstage_ $@.tmp $@
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endif
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@ -51,7 +51,7 @@ HOSTCXX:=CCC_CXX="$(HOSTCXX)" $(CXX)
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ROMCC=CCC_CC="$(ROMCC_BIN)" $(CC)
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endif
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COREBOOT_STANDARD_STAGES := bootblock verstage romstage ramstage
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COREBOOT_STANDARD_STAGES := bootblock romstage ramstage
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ARCHDIR-i386 := x86
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ARCHDIR-x86_32 := x86
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