check in the current code for IBM/E325, can somebody help to fix it ?
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo
parent
1e1a34fdd1
commit
5782d273eb
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@ -354,15 +354,13 @@ void compute_allocate_resource(
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resource->flags &= ~IORESOURCE_STORED;
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base += size;
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printk_spew(
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"%s %02x * [0x%08lx - 0x%08lx] %s\n",
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printk_spew("%s %02x * [0x%08lx - 0x%08lx] %s\n",
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dev_path(dev),
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resource->index,
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resource->base, resource->base + resource->size -1,
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resource->index, resource->base,
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resource->base + resource->size - 1,
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(resource->flags & IORESOURCE_IO)? "io":
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(resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
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}
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}
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/* A pci bridge resource does not need to be a power
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* of two size, but it does have a minimum granularity.
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@ -421,6 +419,7 @@ static void allocate_vga_resource(void)
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/** Assign the computed resources to the bridges and devices on the bus.
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* Recurse to any bridges found on this bus first. Then do the devices
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* on this bus.
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*
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* @param bus Pointer to the structure for this bus
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*/
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void assign_resources(struct bus *bus)
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@ -443,15 +442,23 @@ void assign_resources(struct bus *bus)
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printk_debug("ASSIGNED RESOURCES, bus %d\n", bus->secondary);
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}
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/**
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* @brief Enable the resources for a specific device
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*
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* @param dev the device whose resources are to be enabled
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*
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* Enable resources of the device by calling the device specific
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* enable_resources() method.
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*
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* The parent's resources should be enabled first to avoid having enabling
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* order problem. This is done by calling the parent's enable_resources()
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* method and let the method to call it's children's enable_resoruces() via
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* enable_childrens_resources().
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*/
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void enable_resources(struct device *dev)
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{
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/* Enable the resources for a specific device.
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* The parents resources should be enabled first to avoid
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* having enabling ordering problems.
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*/
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if (!dev->ops || !dev->ops->enable_resources) {
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printk_err("%s missing enable_resources\n",
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dev_path(dev));
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printk_err("%s missing enable_resources\n", dev_path(dev));
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return;
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}
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if (!dev->enable) {
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@ -464,12 +471,13 @@ void enable_resources(struct device *dev)
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* @brief Determine the existence of dynamic devices and construct dynamic
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* device tree.
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*
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* Start for the root device 'dev_root', scan the buses in the system, build
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* the dynamic device tree according to the result of the probe.
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* Start for the root device 'dev_root', scan the buses in the system
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* recursively, build the dynamic device tree according to the result
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* of the probe.
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*
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* This function have no idea how to scan and probe the buses and devices at
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* all. It depends on the bus/device specific scan_bus() method to do it.
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* The scan_bus() function also have to create the device structure and attach
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* This function has no idea how to scan and probe buses and devices at all.
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* It depends on the bus/device specific scan_bus() method to do it. The
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* scan_bus() function also have to create the device structure and attach
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* it to the device tree.
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*/
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void dev_enumerate(void)
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@ -488,9 +496,14 @@ void dev_enumerate(void)
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/**
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* @brief Configure devices on the devices tree.
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*
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* Starting at the root, compute what resources are needed and allocate them.
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* I/O starts at PCI_IO_START. Since the assignment is hierarchical we
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* set the values into the dev_root struct.
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* Starting at the root of the dynamic device tree, travel recursively,
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* compute resources needed by each device and allocate them.
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*
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* I/O resources start at DEVICE_IO_START and grow upward. MEM resources start
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* at DEVICE_MEM_START and grow downward.
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*
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* Since the assignment is hierarchical we set the values into the dev_root
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* struct.
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*/
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void dev_configure(void)
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{
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@ -44,8 +44,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
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bus_isa++;
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}
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else {
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} else {
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printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
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bus_8111_1 = 4;
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@ -55,20 +54,15 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
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if (dev) {
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bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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} else {
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printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
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bus_8131_1 = 2;
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}
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/* 8131-2 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
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if (dev) {
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bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
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}
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else {
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} else {
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printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
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bus_8131_2 = 3;
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@ -82,19 +76,18 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_bus(mc, bus_isa, "ISA ");
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/* IOAPIC handling */
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smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
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{
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device_t dev;
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uint32_t base;
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/* 8131 apic 3 */
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/* 8131-1 apic #3 */
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dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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smp_write_ioapic(mc, 0x03, 0x11, base);
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}
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/* 8131 apic 4 */
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/* 8131-2 apic #4 */
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dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
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if (dev) {
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base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
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@ -143,46 +136,34 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_isa, 0x00, MP_APIC_ALL, 0x01);
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/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
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/* On board nics */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x03<<2)|0, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x04<<2)|0, 0x02, 0x13);
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/* PCI Slot 1 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (1<<2)|3, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x01<<2)|3, 0x02, 0x10);
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/* PCI Slot 2 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_2, (2<<2)|3, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_2, (0x02<<2)|3, 0x02, 0x11);
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/* PCI Slot 3 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (1<<2)|3, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|0, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|1, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|2, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (0x01<<2)|3, 0x02, 0x10);
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/* PCI Slot 4 */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (2<<2)|3, 0x02, 0x11);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|0, 0x02, 0x12);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|1, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|2, 0x02, 0x10);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_8131_1, (2<<2)|3, 0x02, 0x11);
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/* PCI Slot 5 */
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#warning "FIXME get the irqs right, it's just hacked to work for now"
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@ -206,17 +187,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8111_1, (4<<2)|3, 0x02, 0x13);
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/* On board nics */
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (3<<2)|0, 0x02, 0x13);
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smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
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bus_8131_1, (4<<2)|0, 0x02, 0x13);
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/* There is no extension information... */
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/* Compute the checksums */
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mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
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mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
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printk_debug("Wrote the mp table end at: %p - %p\n",
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mc, smp_next_mpe_entry(mc));
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@ -258,13 +258,13 @@ northbridge amd/amdk8 "mc0"
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131" link 0
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southbridge amd/amd8131 "amd8131" link 1
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111" link 0
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southbridge amd/amd8111 "amd8111" link 1
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pci 0:0.0
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pci 0:1.0 on
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pci 0:1.1 on
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@ -314,7 +314,7 @@ northbridge amd/amdk8 "mc1"
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end
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cpu k8 "cpu0"
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register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
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register "across" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
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end
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cpu k8 "cpu1"
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@ -173,19 +173,20 @@ static void main(void)
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console_init();
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setup_ibm_e325_resource_map();
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xA0);
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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#if 0
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#if 1
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print_pci_devices();
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#endif
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu[0]);
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#endif
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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@ -196,7 +197,6 @@ static void main(void)
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dump_pci_device(PCI_DEV(0, 0x18, 2));
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#endif
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#if 0
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/* Check the first 1M */
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ram_check(0x00000000, 0x001000000);
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@ -281,6 +281,6 @@ static void enumerate(struct chip *chip)
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}
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struct chip_control mainboard_arima_hdama_control = {
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.enumerate = enumerate,
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.name = "Arima HDAMA mainboard ",
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.name = "IBM E325 mainboard ",
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};
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@ -1,103 +1,3 @@
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#if 0
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=================== CPU0 ===================
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RAM 0x0(0x3,0x3f0000):
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0x000:0x3f00(no interleave, bogus), CP0, s: WE
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RAM 0x1(0x400003,0x7f0001):
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0x4000:0x7f00(no interleave, bogus), CP1, s: WE
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RAM 0x2(0x800000,0x2):
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0x8000:0x000(no interleave, bogus), CP2, s: NO WE
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RAM 0x3(0x800000,0x3):
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0x8000:0x000(no interleave, bogus), CP3, s: NO WE
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RAM 0x4(0x800000,0x4):
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0x8000:0x000(no interleave, bogus), CP4, s: NO WE
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RAM 0x5(0x800000,0x5):
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0x8000:0x000(no interleave, bogus), CP5, s: NO WE
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RAM 0x6(0x800000,0x6):
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0x8000:0x000(no interleave, bogus), CP6, s: NO WE
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RAM 0x7(0x800000,0x7):
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0x8000:0x000(no interleave, bogus), CP7, s: NO WE
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MMIO 0x0(0xfc0003,0xfe2f10):
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0xfc000000:0xfe2f0000, HT1 CP0, WE:RE
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MMIO 0x1(0x0,0x0):
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0x00000:0x00000, HT0 CP0, NO WE:NO RE
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MMIO 0x2(0x0,0x0):
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0x00000:0x00000, HT0 CP0, NO WE:NO RE
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MMIO 0x3(0x0,0x0):
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0x00000:0x00000, HT0 CP0, NO WE:NO RE
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MMIO 0x4(0xfec003,0xfec010):
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0xfec00000:0xfec00000, HT1 CP0, WE:RE
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MMIO 0x5(0xa03,0xb10):
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0xa0000:0xb0000, HT1 CP0, WE:RE
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MMIO 0x6(0xfed003,0xfed010):
|
||||
0xfed00000:0xfed00000, HT1 CP0, WE:RE
|
||||
MMIO 0x7(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
PCIO 0x0(0x33,0x1fff010):
|
||||
0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
|
||||
PCIO 0x1(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
PCIO 0x2(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
PCIO 0x3(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
CONF 0x0(0xff000103):
|
||||
0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
|
||||
CONF 0x1(0xffff0060):
|
||||
0xff0000:0x00000, HT0 CP6, Dev number compare enable NO WE:NO RE
|
||||
CONF 0x2(0xffff0324):
|
||||
0xff0000:0x00000, HT3 CP2, Dev number compare enable NO WE:NO RE
|
||||
CONF 0x3(0xffff0204):
|
||||
0xff0000:0x00000, HT2 CP0, Dev number compare enable NO WE:NO RE
|
||||
=================== CPU1 ===================
|
||||
RAM 0x0(0x3,0x3f0000):
|
||||
0x000:0x3f00(no interleave, bogus), CP0, s: WE
|
||||
RAM 0x1(0x400003,0x7f0001):
|
||||
0x4000:0x7f00(no interleave, bogus), CP1, s: WE
|
||||
RAM 0x2(0x800000,0x2):
|
||||
0x8000:0x000(no interleave, bogus), CP2, s: NO WE
|
||||
RAM 0x3(0x800000,0x3):
|
||||
0x8000:0x000(no interleave, bogus), CP3, s: NO WE
|
||||
RAM 0x4(0x800000,0x4):
|
||||
0x8000:0x000(no interleave, bogus), CP4, s: NO WE
|
||||
RAM 0x5(0x800000,0x5):
|
||||
0x8000:0x000(no interleave, bogus), CP5, s: NO WE
|
||||
RAM 0x6(0x800000,0x6):
|
||||
0x8000:0x000(no interleave, bogus), CP6, s: NO WE
|
||||
RAM 0x7(0x800000,0x7):
|
||||
0x8000:0x000(no interleave, bogus), CP7, s: NO WE
|
||||
MMIO 0x0(0xfc0003,0xfe2f10):
|
||||
0xfc000000:0xfe2f0000, HT1 CP0, WE:RE
|
||||
MMIO 0x1(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
MMIO 0x2(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
MMIO 0x3(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
MMIO 0x4(0xfec003,0xfec010):
|
||||
0xfec00000:0xfec00000, HT1 CP0, WE:RE
|
||||
MMIO 0x5(0xa03,0xb10):
|
||||
0xa0000:0xb0000, HT1 CP0, WE:RE
|
||||
MMIO 0x6(0xfed003,0xfed010):
|
||||
0xfed00000:0xfed00000, HT1 CP0, WE:RE
|
||||
MMIO 0x7(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
PCIO 0x0(0x33,0x1fff010):
|
||||
0x00000:0x1fff0000, HT1 CP0, ISA VGA WE:RE
|
||||
PCIO 0x1(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
PCIO 0x2(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
PCIO 0x3(0x0,0x0):
|
||||
0x00000:0x00000, HT0 CP0, NO WE:NO RE
|
||||
CONF 0x0(0xff000103):
|
||||
0x00000:0x00000, HT1 CP0, Dev number compare enable WE:RE
|
||||
CONF 0x1(0xffff0200):
|
||||
0xff0000:0x00000, HT2 CP0, NO WE:NO RE
|
||||
CONF 0x2(0xffff0370):
|
||||
0xff0000:0x00000, HT3 CP7, Dev number compare enable NO WE:NO RE
|
||||
CONF 0x3(0xffff0330):
|
||||
0xff0000:0x00000, HT3 CP3, Dev number compare enable NO WE:NO RE
|
||||
#endif
|
||||
/*
|
||||
* IBM E325 needs a different resource map
|
||||
*
|
||||
|
|
@ -237,22 +137,27 @@ static void setup_ibm_e325_resource_map(void)
|
|||
* This field defines the upper address bits of a 40bit address
|
||||
* that defines the start of memory-mapped I/O region i
|
||||
*/
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfe2f10,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfc0003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfec010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfec003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xb10,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xa03,
|
||||
PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0xfed010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0xfed003,
|
||||
PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xbc), 0x48, 0x0,
|
||||
// PCI_ADDR(0, 0x18, 1, 0xb8), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0xfec010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0xfec003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xb4), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xb0), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0xb10,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0xa03,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xac), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa8), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0xfed010,
|
||||
PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0xfed003,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa4), 0x48, 0x0,
|
||||
//PCI_ADDR(0, 0x18, 1, 0xa0), 0xf0, 0x0,
|
||||
|
||||
PCI_ADDR(0, 0x18, 1, 0x9c), 0x48, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x98), 0xf0, 0x0,
|
||||
PCI_ADDR(0, 0x18, 1, 0x94), 0x48, 0x0,
|
||||
|
|
|
|||
|
|
@ -507,7 +507,7 @@ static void coherent_ht_finalize(unsigned cpus)
|
|||
* registers on Hammer A0 revision.
|
||||
*/
|
||||
|
||||
#if 0
|
||||
#if 1
|
||||
print_debug("coherent_ht_finalize\r\n");
|
||||
#endif
|
||||
rev_a0 = is_cpu_rev_a0();
|
||||
|
|
@ -537,15 +537,14 @@ static void coherent_ht_finalize(unsigned cpus)
|
|||
pci_write_config32(dev, 0x68, val);
|
||||
|
||||
if (rev_a0) {
|
||||
print_debug("shit it is an old cup\n");
|
||||
pci_write_config32(dev, 0x94, 0);
|
||||
pci_write_config32(dev, 0xb4, 0);
|
||||
pci_write_config32(dev, 0xd4, 0);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
#if 0
|
||||
#if 1
|
||||
print_debug("done\r\n");
|
||||
#endif
|
||||
}
|
||||
|
|
@ -619,7 +618,8 @@ static int optimize_link_read_pointers(unsigned cpus, int needs_reset)
|
|||
link_type = pci_read_config32(f0_dev, reg);
|
||||
if (link_type & LinkConnected) {
|
||||
cmd &= 0xff << (link *8);
|
||||
/* FIXME this assumes the device on the other side is an AMD device */
|
||||
/* FIXME this assumes the device on the other
|
||||
* side is an AMD device */
|
||||
cmd |= 0x25 << (link *8);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,8 +85,7 @@ struct mem_range *sizeram(void)
|
|||
}
|
||||
if ((mem[idx - 1].basek + mem[idx - 1].sizek) <= 4*1024*1024) {
|
||||
idx -= 1;
|
||||
}
|
||||
else {
|
||||
} else {
|
||||
mem[idx - 1].basek = 4*1024*1024;
|
||||
mem[idx - 1].sizek -= (4*1024*1024 - mmio_basek);
|
||||
}
|
||||
|
|
@ -162,15 +161,17 @@ static unsigned int amdk8_nodeid(device_t dev)
|
|||
return (dev->path.u.pci.devfn >> 3) - 0x18;
|
||||
}
|
||||
|
||||
|
||||
static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
|
||||
{
|
||||
unsigned nodeid;
|
||||
unsigned link;
|
||||
|
||||
nodeid = amdk8_nodeid(dev);
|
||||
|
||||
#if 1
|
||||
printk_debug("amdk8_scan_chains max: %d starting...\n", max);
|
||||
#endif
|
||||
|
||||
for (link = 0; link < dev->links; link++) {
|
||||
uint32_t link_type;
|
||||
uint32_t busses, config_busses;
|
||||
|
|
@ -188,7 +189,8 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
|
|||
if (!(link_type & NonCoherent)) {
|
||||
continue;
|
||||
}
|
||||
/* See if there is an available configuration space mapping register in function 1. */
|
||||
/* See if there is an available configuration space mapping register
|
||||
* in function 1. */
|
||||
free_reg = 0;
|
||||
for(config_reg = 0xe0; config_reg <= 0xec; config_reg += 4) {
|
||||
uint32_t config;
|
||||
|
|
@ -206,14 +208,15 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
|
|||
if (free_reg && (config_reg > 0xec)) {
|
||||
config_reg = free_reg;
|
||||
}
|
||||
/* If we can't find an available configuration space mapping register skip this bus */
|
||||
/* If we can't find an available configuration space mapping
|
||||
* register skip this bus */
|
||||
if (config_reg > 0xec) {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Set up the primary, secondary and subordinate bus numbers. We have
|
||||
* no idea how many busses are behind this bridge yet, so we set the subordinate
|
||||
* bus number to 0xff for the moment.
|
||||
/* Set up the primary, secondary and subordinate bus numbers.
|
||||
* We have no idea how many busses are behind this bridge yet,
|
||||
* so we set the subordinate bus number to 0xff for the moment.
|
||||
*/
|
||||
dev->link[link].secondary = ++max;
|
||||
dev->link[link].subordinate = 0xff;
|
||||
|
|
@ -225,8 +228,8 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
|
|||
config_busses = f1_read_config32(config_reg);
|
||||
|
||||
/* Configure the bus numbers for this bridge: the configuration
|
||||
* transactions will not be propagates by the bridge if it is not
|
||||
* correctly configured
|
||||
* transactions will not be propagates by the bridge if it is
|
||||
* not correctly configured
|
||||
*/
|
||||
busses &= 0xff000000;
|
||||
busses |= (((unsigned int)(dev->bus->secondary) << 0) |
|
||||
|
|
@ -244,24 +247,29 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
|
|||
f1_write_config32(config_reg, config_busses);
|
||||
|
||||
#if 1
|
||||
printk_debug("Hyper transport scan link: %d max: %d\n", link, max);
|
||||
printk_debug("Hyper transport scan link: %d max: %d\n",
|
||||
link, max);
|
||||
#endif
|
||||
/* Now we can scan all of the subordinate busses i.e. the chain on the hypertranport link */
|
||||
|
||||
/* Now we can scan all of the subordinate busses i.e. the
|
||||
* chain on the hypertranport link */
|
||||
max = hypertransport_scan_chain(&dev->link[link], max);
|
||||
|
||||
#if 1
|
||||
printk_debug("Hyper transport scan link: %d new max: %d\n", link, max);
|
||||
printk_debug("Hyper transport scan link: %d new max: %d\n",
|
||||
link, max);
|
||||
#endif
|
||||
|
||||
/* We know the number of busses behind this bridge. Set the subordinate
|
||||
* bus number to it's real value
|
||||
/* We know the number of busses behind this bridge. Set the
|
||||
* subordinate bus number to it's real value
|
||||
*/
|
||||
dev->link[link].subordinate = max;
|
||||
busses = (busses & 0xff00ffff) |
|
||||
((unsigned int) (dev->link[link].subordinate) << 16);
|
||||
pci_write_config32(dev, dev->link[link].cap + 0x14, busses);
|
||||
|
||||
config_busses = (config_busses & 0x00ffffff) | (dev->link[link].subordinate << 24);
|
||||
config_busses = (config_busses & 0x00ffffff) |
|
||||
(dev->link[link].subordinate << 24);
|
||||
f1_write_config32(config_reg, config_busses);
|
||||
#if 1
|
||||
printk_debug("Hypertransport scan link done\n");
|
||||
|
|
@ -273,7 +281,6 @@ static unsigned int amdk8_scan_chains(device_t dev, unsigned int max)
|
|||
return max;
|
||||
}
|
||||
|
||||
|
||||
static unsigned amdk8_find_iopair(unsigned nodeid, unsigned link)
|
||||
{
|
||||
unsigned free_reg, reg;
|
||||
|
|
@ -305,6 +312,7 @@ static unsigned amdk8_find_iopair(unsigned nodeid, unsigned link)
|
|||
static unsigned amdk8_find_mempair(unsigned nodeid, unsigned link)
|
||||
{
|
||||
unsigned free_reg, reg;
|
||||
|
||||
free_reg = 0;
|
||||
for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
|
||||
uint32_t base, limit;
|
||||
|
|
@ -379,7 +387,8 @@ static void amdk8_read_resources(device_t dev)
|
|||
}
|
||||
}
|
||||
|
||||
static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned nodeid)
|
||||
static void amdk8_set_resource(device_t dev, struct resource *resource,
|
||||
unsigned nodeid)
|
||||
{
|
||||
unsigned long rbase, rlimit;
|
||||
unsigned reg, link;
|
||||
|
|
@ -402,7 +411,8 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
|
|||
rbase = resource->base;
|
||||
|
||||
/* Get the limit (rounded up) */
|
||||
rlimit = rbase + ((resource->size + resource->align - 1UL) & ~(resource->align -1)) - 1UL;
|
||||
rlimit = rbase + ((resource->size + resource->align - 1UL) &
|
||||
~(resource->align -1)) - 1UL;
|
||||
|
||||
/* Get the register and link */
|
||||
reg = resource->index & ~3;
|
||||
|
|
@ -431,8 +441,7 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
|
|||
|
||||
f1_write_config32(reg + 0x4, limit);
|
||||
f1_write_config32(reg, base);
|
||||
}
|
||||
else if (resource->flags & IORESOURCE_MEM) {
|
||||
} else if (resource->flags & IORESOURCE_MEM) {
|
||||
uint32_t base, limit;
|
||||
compute_allocate_resource(&dev->link[link], resource,
|
||||
IORESOURCE_MEM, IORESOURCE_MEM);
|
||||
|
|
@ -449,12 +458,8 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
|
|||
f1_write_config32(reg, base);
|
||||
}
|
||||
resource->flags |= IORESOURCE_STORED;
|
||||
printk_debug(
|
||||
"%s %02x <- [0x%08lx - 0x%08lx] node %d link %d %s\n",
|
||||
dev_path(dev),
|
||||
reg,
|
||||
rbase, rlimit,
|
||||
nodeid, link,
|
||||
printk_debug("%s %02x <- [0x%08lx - 0x%08lx] node %d link %d %s\n",
|
||||
dev_path(dev), reg, rbase, rlimit, nodeid, link,
|
||||
(resource->flags & IORESOURCE_IO)? "io": "mem");
|
||||
}
|
||||
|
||||
|
|
@ -538,14 +543,15 @@ static void amdk8_enable_resources(struct device *dev)
|
|||
}
|
||||
|
||||
if (vgalink != 1) {
|
||||
/* now find the IOPAIR that goes to vgalink and set the vga enable in the base part (0x30) */
|
||||
/* now allocate an MMIOPAIR and point it to the CPU0, LINK=vgalink */
|
||||
/* now set IORR1 so it has a hole for the 0xa0000-0xcffff region */
|
||||
/* now find the IOPAIR that goes to vgalink and set the vga
|
||||
* enable in the base part (0x30) */
|
||||
/* now allocate an MMIOPAIR and point it to the CPU0,
|
||||
* LINK=vgalink */
|
||||
/* now set IORR1 so it has a hole for the 0xa0000-0xcffff
|
||||
* region */
|
||||
}
|
||||
#endif
|
||||
|
||||
pci_dev_enable_resources(dev);
|
||||
//enable_childrens_resources(dev);
|
||||
}
|
||||
|
||||
static struct device_operations northbridge_operations = {
|
||||
|
|
|
|||
Loading…
Reference in New Issue