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mb/google/zoombini: Enable NVMe 

BUG=b:72120814
BRANCH=master
TEST=none

Change-Id: I64ab38dda78345c1f3d7d3f2bf3cb04c19290ceb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/25256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2018-03-16 12:29:48 -07:00 committed by Patrick Georgi
parent 25c1781cba
commit 579d4550d2
1 changed files with 6 additions and 1 deletions
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7
src/mainboard/google/zoombini/variants/baseboard/devicetree.cb
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@ -51,6 +51,11 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
# Enable Root port 8 (PCIe port 9) for NVMe
register "PcieRpEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "8"
register "PcieClkSrcClkReq[3]" = "3"
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device device pci 02.0 on end # Integrated Graphics Device
@ -81,7 +86,7 @@ chip soc/intel/cannonlake
device pci 1c.5 off end # PCI Express Port 6 device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7 device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8 device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 off end # PCI Express Port 9 device pci 1d.0 on end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10 device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11 device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12 device pci 1d.3 off end # PCI Express Port 12