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sb/intel/lynxpoint/acpi: Add missing USB ports 

Broadwell has these devices, so add them to Lynx Point as well. This is
done in preparation to have Broadwell boards use Lynx Point ACPI code.

Change-Id: Id66f169070cdfe3a6d166ca18916d4ddaf4a5fea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-29 13:24:57 +01:00 committed by Patrick Georgi
parent acd65dddbd
commit 57a2a3ba93
1 changed files with 3 additions and 0 deletions
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src/southbridge/intel/lynxpoint/acpi/xhci.asl
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@ -337,9 +337,12 @@ Device (XHCI)
Device (PRT5) { Name (_ADR, 5) } // USB Port 4 Device (PRT5) { Name (_ADR, 5) } // USB Port 4
Device (PRT6) { Name (_ADR, 6) } // USB Port 5 Device (PRT6) { Name (_ADR, 6) } // USB Port 5
Device (PRT7) { Name (_ADR, 7) } // USB Port 6 Device (PRT7) { Name (_ADR, 7) } // USB Port 6
Device (PRT8) { Name (_ADR, 8) } // USB Port 7
Device (SSP1) { Name (_ADR, 10) } // USB Port 10 Device (SSP1) { Name (_ADR, 10) } // USB Port 10
Device (SSP2) { Name (_ADR, 11) } // USB Port 11 Device (SSP2) { Name (_ADR, 11) } // USB Port 11
Device (SSP3) { Name (_ADR, 12) } // USB Port 12 Device (SSP3) { Name (_ADR, 12) } // USB Port 12
Device (SSP4) { Name (_ADR, 13) } // USB Port 13 Device (SSP4) { Name (_ADR, 13) } // USB Port 13
Device (SSP5) { Name (_ADR, 14) } // USB Port 14
Device (SSP6) { Name (_ADR, 15) } // USB Port 15
} }
} }