Doc/releases/4.18: Improve several small things
Add a missing period, use "SoC" with lowercase 'o' to refer to a "System on a Chip", fix up the redundant "CRB board" expression (that stands for "Customer Reference Board board"), switch the position of a verb and its adverb ("never was" ---> "was never") to sound more natural, and replace "depreciate" with "deprecate" for semantic correctness. Change-Id: Ic821a9030d4ff32c76765f51f1feb0f5503d4cc0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68330 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -19,7 +19,7 @@ coreboot uses TianoCore interchangeably with EDK II, and whilst the
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meaning is generally clear, it's not the payload it uses. Consequentially,
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Tianocore has been renamed to EDK II (2).
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The option to use the already depreciated CorebootPayloadPkg has been
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The option to use the already deprecated CorebootPayloadPkg has been
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removed.
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Recent changes to both coreboot and edk2 means that UefiPayloadPkg
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@ -32,7 +32,7 @@ seems to work on all hardware. It has been tested on:
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CorebootPayloadPkg can still be found [here](https://github.com/MrChromebox/edk2/tree/coreboot_fb).
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The recommended option to use is `EDK2_UEFIPAYLOAD_MRCHROMEBOX` as
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`EDK2_UEFIPAYLOAD_OFFICIAL` will no longer work on any SOC.
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`EDK2_UEFIPAYLOAD_OFFICIAL` will no longer work on any SoC.
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Plans for Code Deprecation
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--------------------------
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@ -41,12 +41,12 @@ Plans for Code Deprecation
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### Intel Icelake
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Intel Icelake code will be removed with the release 4.19. This consists
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of the Intel Icelake SOC and Intel Icelake RVP mainboard
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of the Intel Icelake SoC and Intel Icelake RVP mainboard.
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Intel Icelake is unmaintained. Also, the only user of this platform ever
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was the CRB board. From the looks of it the code never was ready for
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production as only engineering sample CPUIDs are supported. This reduces
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the maintanence overhead for the coreboot project.
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was the Intel CRB (Customer Reference Board). From the looks of it the
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code was never ready for production as only engineering sample CPUIDs are
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supported. This reduces the maintanence overhead for the coreboot project.
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### Intel Quark
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