mb/google/guybrush: Add helpers for cbi fw_config settings
Turn on CBI and add helper functions for determining the board configuration from the firmware config settings in CBI. BUG=b:187316460 TEST=Built Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I212e7f413b4d8a7d15122cde90100a0ec28e88a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54639 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS
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select ELOG
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select ELOG
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select ELOG_GSMI
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select ELOG_GSMI
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select FW_CONFIG
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select FW_CONFIG
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select FW_CONFIG_SOURCE_CHROMEEC_CBI
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select GOOGLE_SMBIOS_MAINBOARD_VERSION
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_RESUME
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select HAVE_EM100_SUPPORT
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select HAVE_EM100_SUPPORT
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@ -1,9 +1,11 @@
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bootblock-y += gpio.c
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bootblock-y += gpio.c
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bootblock-y += helpers.c
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bootblock-y += helpers.c
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romstage-y += helpers.c
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romstage-y += tpm_tis.c
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romstage-y += tpm_tis.c
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ramstage-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += helpers.c
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ramstage-y += tpm_tis.c
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ramstage-y += tpm_tis.c
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verstage-y += gpio.c
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verstage-y += gpio.c
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@ -2,11 +2,20 @@
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#include <baseboard/variants.h>
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#include <baseboard/variants.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <fw_config.h>
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#include <soc/iomap.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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bool variant_has_fpmcu(void)
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static bool variant_has_device_enabled(const struct device_path *device_path, size_t path_length)
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{
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const struct device *dev =
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find_dev_nested_path(all_devices->link_list, device_path, path_length);
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return is_dev_enabled(dev);
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}
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__weak bool variant_has_fpmcu(void)
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{
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{
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DEVTREE_CONST struct device *mmio_dev = NULL;
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static const struct device_path fpmcu_path[] = {
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static const struct device_path fpmcu_path[] = {
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{
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{
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.type = DEVICE_PATH_MMIO,
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.type = DEVICE_PATH_MMIO,
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@ -18,11 +27,18 @@ bool variant_has_fpmcu(void)
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.generic.subid = 0
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.generic.subid = 0
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},
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},
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};
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};
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mmio_dev = find_dev_nested_path(
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all_devices->link_list, fpmcu_path, ARRAY_SIZE(fpmcu_path));
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if (mmio_dev == NULL)
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return variant_has_device_enabled(fpmcu_path, ARRAY_SIZE(fpmcu_path));
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return false;
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}
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return mmio_dev->enabled;
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__weak bool variant_has_pcie_wwan(void)
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{
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static const struct device_path pcie_wwan_path[] = {
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{
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.type = DEVICE_PATH_PCI,
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.pci.devfn = PCIE_GPP_2_2_DEVFN,
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},
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};
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return variant_has_device_enabled(pcie_wwan_path, ARRAY_SIZE(pcie_wwan_path));
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}
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}
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@ -28,4 +28,6 @@ void variant_fpmcu_reset(void);
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bool variant_has_fpmcu(void);
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bool variant_has_fpmcu(void);
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bool variant_has_pcie_wwan(void);
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#endif /* __BASEBOARD_VARIANTS_H__ */
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#endif /* __BASEBOARD_VARIANTS_H__ */
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@ -33,6 +33,9 @@ end
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chip soc/amd/cezanne
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chip soc/amd/cezanne
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device domain 0 on
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device domain 0 on
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device ref gpp_bridge_2 on
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probe WWAN WWAN_FM350GL
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end # WWAN
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end # domain
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end # domain
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register "slow_ppt_limit_mW" = "25000"
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register "slow_ppt_limit_mW" = "25000"
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